package BACK

import chisel3._
import chisel3.util._



class ShinTopIO extends Bundle{

  val dDatIn   = Input(Bool())
  val dDatOut  = Output(Bool())
  val uDatIn   = Input(Bool())
  val uDatOut  = Output(Bool())

  val multiCLK = Input(Vec(16, Bool()))

  val iqspi = new QSPIInterfaceIO
  val ospi = new SSPIInterfaceIO
  val oqspi = new QSPIInterfaceIO

  val iSync = Output(Vec(4, Bool()))

  val isSoftReset = Output(Bool())

  val interrupt = Output(Bool())

  val latchPin = Input(Vec(2, Bool()))
  val hwSerial = Input(UInt(48.W))
  val uniCode = Input(UInt(64.W))

  val pllCtrl = Output(UInt(32.W))
  val xtal    = Output(UInt(12.W))
  val anamuxSel = Output(UInt(5.W))
  val ldo2p5 = Output(UInt(8.W))
  val ldo1p1 = Output(UInt(8.W))
  val refTop = Output(UInt(3.W))
  val bias   = Output(UInt(2.W))

  val spiSel  = Output(UInt(2.W))
}


class ShinTop extends Module with RequireAsyncReset{


  
  downCDRIn.multiCLK := io.multiCLK
  upCDRIn.multiCLK   := io.multiCLK


  val downCDROut = Module(new CDROut)
  val upCDROut   = Module(new CDROut)
  val downCDRIn = Module(new MPCDRIn)
  val upCDRIn   = Module(new MPCDRIn)






  when( interface.io.cReg.modeSel === false.B ){ //slave
    when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
      downCDRIn.io.serDat  := false.B
      upCDRIn.io.serDat  := false.B
      when( slaveParser.io.isLoop ){ //回环
        io.dDatOut := false.B
        io.uDatOut := io.dDatIn
      } .otherwise{ //非回环
        io.dDatOut := io.dDatIn
        io.uDatOut := io.uDatIn      
      }
    } .otherwise{ //无硬件错误
      when( slaveParser.io.isLoop ){ //回环
        downCDRIn.io.serDat  := io.dDatIn
        upCDRIn.io.serDat    := downCDROut.io.serDat
        io.dDatOut := false.B
        io.uDatOut := upCDROut.io.serDat 
      } .otherwise{ //非回环
        downCDRIn.io.serDat  := io.dDatIn
        upCDRIn.io.serDat    := io.uDatIn
        io.dDatOut := downCDROut.io.serDat
        io.uDatOut := upCDROut.io.serDat
      }
    }
  } .otherwise{ //master
    downCDRIn.io.serDat  := false.B
    upCDRIn.io.serDat    := io.uDatIn
    io.dDatOut := downCDROut.io.serDat
    io.uDatOut := false.B
  }






}