package BACK

import chisel3._
import chisel3.util._


//work in 100MHZ
class CDRInIO extends Bundle{
  val axis = Decoupled(new AXIS_Bundle(8))
  val serDat = Input(Bool())
  val overCLK = Input(Bool())
}


abstract class CDRInBase extends Module{
  def sampleRate: Int = 4
  require( sampleRate == 4 )

  val io: CDRInIO = IO(new CDRInIO)


}

trait CDRInOverSample{ this: CDRInBase =>
  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }



  // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
  // val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
  // val isArbLock = RegInit(false.B)

  // for( i <- 0 until sampleRate ){
  //   arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
  //   when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
  //     isArbLock := true.B
  //     arbSel := i.U
  //   }
  // }

  // when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
  //   isArbLock := false.B
  // }

  // val syncSerDat = 
  //   Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )

  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
  arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) )
  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
  when( sampleReg(0) ^ sampleReg(1) ){
    arbLock := arbCnt
  }

  val asyncSerDat = Mux1H(Seq(
    (arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
    (arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
    (arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
    (arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),

    (arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
    (arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
    (arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
    (arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),

    (arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
    (arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
    (arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
    (arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),

    (arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
    (arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
    (arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
    (arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
  ))


  val syncSerDat = ShiftRegister( asyncSerDat, 2 )



    
}


trait CDRInAxis{ this: CDRInBase =>

  def HeaderByte: Int = 8

  val ETH_PRE = "h55".U(8.W)
  val ETH_SFD = "hD5".U(8.W)

  val STATE_IDLE = 0.U
  val STATE_HEADER = 1.U
  val STATE_PAYLOAD = 2.U

  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, STATE_IDLE )

  val bitCnt = Reg(UInt(4.W))
  val byteCnt = RegInit(0.U(12.W))

  val syncSerDat: Bool
  val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )

  val shiftData = Dualb4b5Decoder(checkSFD(9,0))

  val payloadLen = Reg(UInt(12.W))
  when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( shiftData, 0.U(4.W) )
  } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
  }
  
  stateNext := 
    Mux1H(Seq(
      (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
    ))





  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
    bitCnt := 0.U
  } .otherwise{
    when( bitCnt === 9.U ){
      bitCnt := 0.U
    } .otherwise{
      bitCnt := bitCnt + 1.U
    }
  }

  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
    byteCnt := 0.U
  } .elsewhen( bitCnt === 9.U ){
    when( stateCurr === STATE_HEADER ){
      byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
      assert( byteCnt <= (HeaderByte-1).U )
    } .elsewhen( stateCurr === STATE_PAYLOAD ){
      byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
      assert( byteCnt <= ( payloadLen-1.U ) )
    }
  }





  val axis_valid = RegInit(false.B)
  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
  val axis_tuser = false.B
  val axis_tlast = RegNext( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), false.B )

  io.axis.valid := axis_valid
  io.axis.bits.tdata := axis_tdata
  io.axis.bits.tuser := axis_tuser
  io.axis.bits.tlast := axis_tlast


  when( io.axis.fire ){
    axis_valid := false.B
  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
    axis_valid := true.B
  }

}


class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis