.PHONY:com sim clean

OUTPUT = shin_test
CPU_COUNT := $(shell nproc)

VCS = vcs -sverilog +v2k -timescale=1ns/1ps   \
	-full64                                   \
	-o ${OUTPUT}                              \
	-l compile.log                            \
	-debug_access+none						  \
	+define+VCS_COMPILE						  \
	-fastpartcomp=j${CPU_COUNT}				  \

SIM = ./${OUTPUT} -l run.log

testShin_vcs:
	python3 ./shinTest/gen_pkt.py
	mkdir -p generated/log
	rm -rf generated/log/*
	@echo "Available CPUs: ${CPU_COUNT}"
	${VCS} -f ./shinTest_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py


testShinClk_vcs:
	python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data1.txt
	mv generated/wave.vcd	generated/wave1.vcd
	\
	python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 70 -180 -8b10b
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data2.txt
	mv generated/wave.vcd	generated/wave2.vcd
	\
	python3 ./shinTest/gen_pkt_clk.py --dev1 45 185 --dev3 25 -185 
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data3.txt
	mv generated/wave.vcd	generated/wave3.vcd
	\
	python3 ./shinTest/gen_pkt_clk.py --dev1 60 186 --dev3 15 -186
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data4.txt
	mv generated/wave.vcd	generated/wave4.vcd
	\
	python3 ./shinTest/gen_pkt_clk.py --dev1 80 187 --dev2 30 -187
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data5.txt
	mv generated/wave.vcd	generated/wave5.vcd
	\
	python3 ./shinTest/gen_pkt_clk.py --dev1 70 188 --dev3 223 -188 -8b10b
	mkdir -p generated/log
	rm -rf generated/log/*
	${VCS} -f ./shinTestClk_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py
	mv spi_trans_data.txt generated/spi_trans_data6.txt
	mv generated/wave.vcd	generated/wave6.vcd


testShinMany_vcs:
	python3 ./shinTest/gen_pkt_many_dev.py
	mkdir -p generated/log
	rm -rf generated/log/*
	@echo "Available CPUs: ${CPU_COUNT}"
	${VCS} -f ./shinTest_vcs.f
	${SIM}
	python3 ./shinTest/check_testcase.py

sim:
	${SIM}

testShin:
	./shinTest/gen_pkt.py
	mkdir -p generated/log
	rm -rf generated/log/*
	iverilog -Wall  \
	-o ./generated/shinTest.iverilog  \
	-y ./generated/shin \
	-I ./generated/shin \
	-D RANDOMIZE_REG_INIT \
	./shinTest/ShinTopSpiTb.v
	vvp  -N ./generated/shinTest.iverilog -lxt2  -fst || true
	./shinTest/check_testcase.py

testShinClk:
	./shinTest/gen_pkt_clk.py --dev1 0 200
	mkdir -p generated/log
	rm -rf generated/log/*
	iverilog -Wall  \
	-o ./generated/shinTest_clk.iverilog  \
	-y ./generated/shin \
	-I ./generated/shin \
	-D RANDOMIZE_REG_INIT \
	./shinTest/ShinTopSpiTb_clk.v
	vvp  -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
	./shinTest/check_testcase.py

fstShin:
	gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &

fstShinClk:
	gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &

clean:
	rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*