package BACK

import chisel3._
import chisel3.util._


//work in 100MHZ
class CDRInIO extends Bundle{
  val axis = Decoupled(new AXIS_Bundle(8))
  val serDat = Input(Bool())
  val overCLK = Input(Bool())
}


abstract class CDRInBase extends Module{
  def sampleRate: Int = 4
  // require( sampleRate == 4 )

  // require( (sampleRate % 2) == 1 )

  val io: CDRInIO = IO(new CDRInIO)


}

trait CDRInOverSample{ this: CDRInBase =>
  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
  // val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U


  val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
  val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
  val isArbLock = RegInit(false.B)

  for( i <- 0 until sampleRate ){
    arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
    when( arbShiftData(i) === "h555555".U & ~isArbLock ){
      isArbLock := true.B
      arbSel := i.U
    }

  }

  when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
    isArbLock := false.B
  }






  // val arbResult = 
  //   (sampleReg(3) & sampleReg(2) & sampleReg(1)) |
  //   (sampleReg(3) & sampleReg(2) & sampleReg(0)) |
  //   (sampleReg(3) & sampleReg(1) & sampleReg(0)) |
  //   (sampleReg(2) & sampleReg(1) & sampleReg(0))

  val syncSerDat = ShiftRegister( 
    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
    , 2 )
}


trait CDRInAxis{ this: CDRInBase =>

  def HeaderByte: Int = 4

  val ETH_PRE = "h55".U
  val ETH_SFD = "hD5".U

  val STATE_IDLE = 0.U
  val STATE_HEADER = 1.U
  val STATE_PAYLOAD = 2.U
  val STATE_CRC = 3.U




  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, STATE_IDLE )

  val crcUnit = Module(new crc32_8)
  val crcOut = crcUnit.io.crc
  val crcCmp = Reg(UInt(32.W))

  val bitCnt = Reg(UInt(3.W))
  val byteCnt = RegInit(0.U(16.W))

  val syncSerDat: Bool
  val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)

  val header = Reg(UInt((8*HeaderByte).W))
  val payloadLen = header(31,16)
  val operation  = header(15,8)
  val param      = header( 7,0)

  val isArbLock: Bool
  val checkSFD = ShiftRegister( shiftData, 8 )

  stateNext := 
    Mux1H(Seq(
      (stateCurr === STATE_IDLE)    -> ( Mux( isArbLock & checkSFD === ETH_PRE & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U)  ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD  )), // PAYLOAD
      (stateCurr === STATE_CRC)     -> ( Mux( (byteCnt === 3.U)            & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
    ))





  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align
    bitCnt := 0.U
  } .otherwise{ 
    bitCnt := bitCnt + 1.U
  }

  when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align
    byteCnt := 0.U
  } .elsewhen( bitCnt === 7.U ){
    when( stateCurr === STATE_HEADER ){
      byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
      assert( byteCnt <= (HeaderByte-1).U )
    } .elsewhen( stateCurr === STATE_PAYLOAD ){
      byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
      assert( byteCnt <= ( payloadLen-1.U ) )
    } .elsewhen( stateCurr === STATE_CRC ){
      byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U )
      assert( byteCnt <= 3.U )
    }
  }

  when( stateCurr === STATE_HEADER & bitCnt === 7.U ){
    header := Cat( header( 8*HeaderByte-1-8, 0), shiftData )
  }



  val axis_valid = RegInit(false.B)
  val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
  val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )),  bitCnt === 7.U )
  val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U,                                                 bitCnt === 7.U )

  io.axis.valid := axis_valid
  io.axis.bits.tdata := axis_tdata
  io.axis.bits.tuser := axis_tuser
  io.axis.bits.tlast := axis_tlast


  when( io.axis.fire ){
    axis_valid := false.B
  } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
    axis_valid := true.B
  }

  when( stateCurr === STATE_CRC & bitCnt === 7.U ){
    crcCmp := Cat( shiftData, crcCmp(31,8) )
  }


  crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 7.U )
  crcUnit.io.dataIn   := shiftData
  
  crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle

}


class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis