package BACK

import chisel3._
import chisel3.util._

class LVDS_SLV_Bundle extends Bundle{
  val downstream_rx_data_valid = Input(Bool())
  val downstream_rx_data_out   = Input(UInt(8.W))
  val downstream_rx_crc_valid  = Input(Bool())
  val downstream_rx_crc_err    = Input(Bool())
  val upstream_tx_data_in      = Output(UInt(8.W))
  val upstream_tx_data_ready   = Input(Bool())

  val downstream_rx_cdr_err    = Input(Bool())
  val upstream_rx_cdr_err      = Input(Bool())
}

    
class BackBoardSlvIO extends Bundle{

  val isOnline = Output(Bool())
  val isLast   = Input(Bool())

  val DCIn   = Input(Bool())

  val lvdsSlv = new LVDS_SLV_Bundle
}


abstract class BackBoardSlvBase extends Module{
  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
  
  val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
  val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))

  val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
}


trait BackBoardSlvDown{ this: BackBoardSlvBase =>


  val downCnt = Reg(UInt(6.W))


  when( io.lvdsSlv.downstream_rx_data_valid ){
    downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out
    downCnt := downCnt + 1.U
  } .otherwise{
    downCnt := 0.U
  }



  // when( io.lvdsSlv.downstream_rx_crc_valid ){
  //   when( ~io.lvdsSlv.downstream_rx_crc_err ){
  //     for( i <- 1 until 32 ) {
  //       downReg(i) := downRegTemp(i)
  //     }
  //   }
  // }

  // when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){
  //   for( i <- 1 until 32 ) {
  //     downReg(i) := downRegTemp(i)
  //   }
  // }

}
trait BackBoardSlvUp{ this: BackBoardSlvBase =>

  val upCnt = Reg(UInt(6.W))

  io.lvdsSlv.upstream_tx_data_in := upReg(upCnt)

  when( io.lvdsSlv.upstream_tx_data_ready ){
    when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){
      upCnt := 0.U
    } .otherwise{
      upCnt := upCnt + 1.U
    }
  }


}