package BACK

import chisel3._
import chisel3.util._

class InterfaceIO extends Module{

}

class MasterRegisterBundle extends Bundle{
  val isMstNSlv = Bool()
  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(16.W)

  val isExInfoInit = Bool()
  val isTxReq      = UInt(8.W)
  val txStatus     = UInt(16.W)
  val spiSel       = UInt(2.W)

  val isSoftReset  = Bool()
  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  val intEnable    = UInt(8.W)
  val intMask      = UInt(8.W)
  val intStatus    = UInt(8.W)

  val upRecErrorCnt   = UInt(32.W)
  val downRecErrorCnt = UInt(32.W)

  val upForwardErrorCnt   = UInt(32.W)
  val downForwardErrorCnt = UInt(32.W)

  val qspiErrorCnt   = UInt(32.W)
  val forwardCnt     = UInt(32.W)
  val recByteCnt     = UInt(32.W)
  val forwardByteCnt = UInt(32.W)

  val linkStatus = UInt(8.W)

  val wdtStatus   = UInt(16.W)
  val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val deltaTime = UInt(32.W)
}




abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)






  // val RAMSize: UInt
  // val MMUNum: UInt

  // val nodeSeqAddr = Reg(UInt(16.W))
  // val nodeSetAddr = Reg(UInt(16.W))

  // val softReset = Reg(Bool())
  // val logicAddr = Reg(UInt(30.W))
  // val logicLength = Reg(UInt(16.W))
  // val phyAddr - Reg(UInt(16.W))


}





class Interface extends InterfaceBase{

}