package BACK

import chisel3._
import chisel3.util._




class FSMC_Port_Bundle extends Bundle{

  val ADIn  = Input(UInt(16.W))
  val ADOut = Output(UInt(16.W))
  val ADOEn = Output(Bool())
  val csn   = Input(Bool())
  val rdn   = Input(Bool())
  val wrn   = Input(Bool())
  val advn  = Input(Bool())
}


class BackBoardMstIO extends Bundle{
  val FSMC = new FSMC_Port_Bundle

val reset_calib = Input(Bool())
  val oser_pclk = Input(Bool()) //10M
  val oser_fclk = Input(Bool()) //50M
        val ides_pclk = Input(Bool()) //100M
  val ides_fclk = Input(Bool()) //400M

  val lvds_down_dout = Output(Bool())
  val lvds_up_din    = Input(Bool())

  val cdrErr         = Output(Bool())
  val crcErr         = Output(Bool())
  val linkErr        = Output(Bool())

  val testFail = Output(Bool())
  val testDone = Output(Bool())
}

// class Master_Status_Bundle extends Bundle{
//   val zero = UInt(11.W)
//   val cdrErr         = Bool()
//   val crcErr         = Bool()
//   val linkErr        = Bool()
//   val synchronize    = Bool()
//   val initialization = Bool()
// }

// class Master_Control_Bundle extends Bundle{
//   val zero = UInt(13.W)
//   val transmit       = Bool()
//   val synchronize    = Bool()
//   val initialization = Bool()
// }


class BackBoardMstBase extends Module{ //10M
  val io: BackBoardMstIO = IO(new BackBoardMstIO)

  val lvdsMst = Module(new Lvds_Bus_Master)
  val mirrorDown = Module(new MirrorSRAMDown())
  val mirrorUp   = Module(new MirrorSRAMUp())

  val statusCDRErr  = RegInit( false.B )
  val statusCRCErr  = RegInit( false.B )
  val statusLinkErr = RegInit( false.B )
  val statusSynch   = RegInit( false.B )
  val statusInit    = RegInit( false.B )

  val ctrlTransmit = RegInit( false.B )
  val ctrlCDRErr   = RegInit( false.B )
  val ctrlCRCErr   = RegInit( false.B )
  val ctrlLinkErr  = RegInit( false.B )
  val ctrlSynch    = RegInit( false.B )
  val ctrlInit     = RegInit( false.B )

  val slvNum  = RegInit(0.U(6.W))
  val slvOffLine = RegInit(0.U(6.W))
  val testReg = RegInit("haa55".U(16.W))

  lvdsMst.io.rst_n       := ~reset.asBool
  lvdsMst.io.reset_calib := io.reset_calib
  lvdsMst.io.oser_pclk   := io.oser_pclk
  lvdsMst.io.oser_fclk   := io.oser_fclk
  lvdsMst.io.ides_pclk   := io.ides_pclk
  lvdsMst.io.ides_fclk   := io.ides_fclk

  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
  lvdsMst.io.lvds_up_din := io.lvds_up_din





  mirrorDown.io.clockr := io.oser_pclk.asBool
  mirrorDown.io.clockw := io.ides_pclk.asBool //100M  

  mirrorUp.io.clockw := io.oser_pclk.asBool
  mirrorUp.io.clockr := io.ides_pclk.asBool   //100M



  io.cdrErr  := statusCDRErr
  io.crcErr  := statusCRCErr
  io.linkErr := statusLinkErr

}




trait BackBoardMstFSMC{ this: BackBoardMstBase =>
  io.testDone := DontCare
  io.testFail := DontCare

  val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
  val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
  val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M

  withClockAndReset( io.ides_pclk.asClock, reset ){//100M


    val fsmcCSSync  = ShiftRegisters( ~io.FSMC.csn,  3, false.B, true.B )
    val fsmcRDSync  = ShiftRegisters( ~io.FSMC.rdn,  3, false.B, true.B )
    val fsmcWRSync  = ShiftRegisters( ~io.FSMC.wrn,  3, false.B, true.B )
    val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )  

    io.FSMC.ADOEn := fsmcRDSync(1) & fsmcCSSync(1) & ~fsmcADVSync(1)

    val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )

    val isAccessSRAM = ~latchAddr.extract(10) 
    val isAccessReg  =  latchAddr.extract(10)
    val activeAddr   =  latchAddr(9,0)
    val regOut = Wire(UInt(16.W))


    // val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
    // val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
    



    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(1) & fsmcWRSync(1) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
    mirrorDown.io.addrw  := activeAddr
    mirrorDown.io.dataw  := io.FSMC.ADIn

    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(1) & fsmcRDSync(1) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
    mirrorUp.io.addrr  := activeAddr


    io.FSMC.ADOut   := Mux( isAccessReg, regOut, mirrorUp.io.datar)

    regOut := Mux1H(Seq(
      ( activeAddr === 0.U) -> 
        Cat(
          statusCDRErr ,
          statusCRCErr ,
          statusLinkErr,
          statusSynch  ,
          statusInit
        ),
      ( activeAddr === 1.U) -> 
        Cat(
          ctrlTransmit,
          0.U(1.W),
          0.U(1.W),
          0.U(1.W),
          ctrlSynch,
          ctrlInit
        ),
      ( activeAddr === 2.U) -> slvNum,
      ( activeAddr === 3.U) -> slvOffLine,
      ( activeAddr === 4.U) -> testReg,
    ))


  

    when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){

      isRegRefleshFlip := ~isRegRefleshFlip
      wrRegAddr        := activeAddr
      wrRegData        := io.FSMC.ADIn

    }



  }

  //10M
  val isChkRegReflesh = RegInit(false.B)

  when( isChkRegReflesh =/= isRegRefleshFlip ){
    isChkRegReflesh := ~isChkRegReflesh

    when( wrRegAddr === 0.U ){
      when( wrRegData.extract(4) ){
        statusCDRErr := false.B
      }
      when( wrRegData.extract(3) ){
        statusCRCErr := false.B
      }
      when( wrRegData.extract(2) ){
        statusLinkErr := false.B
      }
    }


    when( wrRegAddr === 1.U ){
      ctrlTransmit := wrRegData.extract(5)

      ctrlSynch    := wrRegData.extract(1)

      when( wrRegData.extract(0) ){
        ctrlInit     := true.B
        statusSynch   := false.B
        statusInit    := false.B        
      }

    }

    when( wrRegAddr === 4.U ){
      testReg := wrRegData
    }

  }

}

trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
  io.FSMC.ADOut := DontCare
  io.FSMC.ADOEn := DontCare

  val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
  when( powerUpCnt === 500.U ){
    ctrlInit := true.B
  }

  val ( _, isTransmitTimeout ) = Counter(Range( 0,520), statusInit, false.B)
  when(isTransmitTimeout){
    ctrlTransmit := true.B
  }


  mirrorDown.io.enw    := true.B
  mirrorDown.io.addrw  := powerUpCnt
  mirrorDown.io.dataw  := "h5555".U

  
  mirrorUp.io.enr    := false.B
  mirrorUp.io.addrr  := 0.U

  val testDone = RegInit(false.B)
  val testFail = RegInit(false.B)
  io.testDone := ~testDone
  io.testFail := ~testFail
}



abstract class BackBoardMstLVDSBase extends BackBoardMstBase 
with BackBoardMstFSMC
// with BackBoardMstSim
{


  val frame_info_update_en = RegInit(false.B)
  val slave_type_num       = RegInit(0.U(8.W))
  val slave_data_length    = RegInit(0.U(8.W))
  val tx_start             = RegInit(false.B)

  lvdsMst.io.frame_info_update_en := frame_info_update_en
  lvdsMst.io.slave_type_num       := slave_type_num
  lvdsMst.io.slave_data_length    := slave_data_length
  lvdsMst.io.tx_start := tx_start

  val stateCur = RegInit(15.U(4.W))
}


trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>

  val isInitCntReset = ( ~RegNext(ctrlInit) & ctrlInit ) | (stateCur === 3.U) | (stateCur === 8.U)
  val ( _, isInitTimeout ) = Counter(Range( 0,5200), ctrlInit, isInitCntReset)
  val synchCnt = Reg(UInt(3.W))


  when(ctrlInit){
    when( isInitTimeout ){

      stateCur := 0.U

      frame_info_update_en := false.B
      slave_type_num       := 0.U
      slave_data_length    := 0.U

      tx_start := false.B
      
    } .elsewhen( stateCur === 0.U ){
      stateCur := 1.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b00".U(2.W), slvNum )
      slave_data_length    := ((8/8)*32-1).U

      tx_start := false.B
    } .elsewhen( stateCur === 1.U ){ // tx start
      stateCur := 2.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 2.U ){

      tx_start := false.B

      when( lvdsMst.io.slave_link_num_valid ){
        slvNum := lvdsMst.io.slave_link_num - 1.U
        stateCur := 3.U
      }

    } .elsewhen( stateCur === 3.U ){
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      slave_data_length    := 0.U

      tx_start := false.B

      stateCur := 4.U
      
    } .elsewhen( stateCur === 4.U ){
      stateCur := 5.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b00".U(2.W), slvNum )
      slave_data_length    := ((8/8)*32-1).U

      tx_start := false.B
    } .elsewhen( stateCur === 5.U ){ // tx start
      stateCur := 6.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 6.U ){

      tx_start := false.B

      when( lvdsMst.io.slave_link_num_valid ){
        when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
          stateCur := 7.U
          // testDone := true.B
          // testFail := false.B
        } .otherwise{
          // testDone := false.B
          // testFail := true.B
          printf("Initialization failed, waitting for timeout!\n")
        }
      }

    } .elsewhen( stateCur === 7.U ){
      when( ctrlSynch ){
        stateCur := 8.U
        synchCnt := 0.U
      } .otherwise{
        statusInit  := true.B
        ctrlInit    := false.B
      }

    } .elsewhen( stateCur === 8.U ){   //synch
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      slave_data_length    := 0.U

      tx_start := false.B

      stateCur := 9.U
      
    } .elsewhen( stateCur === 9.U ){
      stateCur := 10.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b01".U(2.W), slvNum )
      slave_data_length    := ((8/8)*32-1).U

      tx_start := false.B
    } .elsewhen( stateCur === 10.U ){ // tx start
      stateCur := 11.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 11.U ){

      tx_start := false.B

      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
        stateCur := 12.U
        synchCnt := synchCnt + 1.U
      }

    } .elsewhen( stateCur === 12.U ){
      when( synchCnt === 4.U ){
        stateCur := 13.U
      } .otherwise{
        stateCur := 8.U
      }
    } .elsewhen( stateCur === 13.U ){
      statusSynch := true.B
      statusInit  := true.B
      ctrlSynch   := false.B
      ctrlInit    := false.B

    } .elsewhen( stateCur === 15.U ){

    }
    .otherwise{

    }
  }



}


trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>

  val trigger = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)

  // val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )

  when(ctrlTransmit){
    when( trigger ){  //reset
      stateCur := 0.U

      frame_info_update_en := false.B
      slave_type_num       := 0.U
      slave_data_length    := 0.U

      tx_start := false.B
      

    } .elsewhen( stateCur === 0.U  ){ //setting
      stateCur := 1.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b10".U(2.W), slvNum )
      slave_data_length    := ((8/8)*32-1).U

      tx_start := false.B
    } .elsewhen( stateCur === 1.U ){ // tx start
      stateCur := 2.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 2.U ){ //waiting  for busy drop

      tx_start := false.B

      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
        stateCur := 3.U
      }

    } .elsewhen( stateCur === 3.U ){
      ctrlTransmit := false.B
    } .otherwise{

    }
  }


  val addrr = RegInit(0.U(11.W))
  val addrw = RegInit(0.U(11.W))

  when( trigger ){
    addrw := 0.U
  } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
    assert( (stateCur === 2.U) || (stateCur === 3.U) )
    addrw := addrw + 1.U
  }

  when( trigger ){
    addrr := 0.U
  } .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){
    addrr := addrr + 1.U
  }

  mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ctrlTransmit
  lvdsMst.io.tx_data_in := mirrorDown.io.datar
  mirrorDown.io.addrr := addrr
  
  mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & ctrlTransmit
  mirrorUp.io.dataw := lvdsMst.io.rx_data_out
  mirrorUp.io.addrw := addrw

}

trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
  when( lvdsMst.io.closed_loop_err ){
    slvOffLine    := lvdsMst.io.link_err_location(5,0)
    statusLinkErr := true.B
  }

  when( lvdsMst.io.upstream_cdr_err ){
    statusCDRErr := true.B
  }

  when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
    statusCRCErr := true.B
  }

}

class BackBoardMst extends BackBoardMstLVDSBase
with BackBoardMstLVDSInitialization
with BackBoardMstLVDSTransmit
with BackBoardMstLVDSError