package BACK

import chisel3._
import chisel3.util._

class AXIS_Bundle(dw: Int) extends Bundle{
  val tdata = UInt(dw.W)
  val tlast = Bool()
  val tuser = Bool()
}

//work in 100MHZ
class CDROutIO extends Bundle{
  val axis = Flipped(Decoupled(new AXIS_Bundle(8))) 
  val serDat = Output(Bool())
}



class CDROut extends Module{
  val io: CDROutIO = IO(new CDROutIO)

  val crcUnit = Module(new crc32_8)

  def STATE_IDLE  = 0.U
  def STATE_PREAMBLE = 1.U
  def STATE_PAYLOAD = 2.U
  def STATE_FCS = 3.U


  val ETH_PRE = "h55".U
  val ETH_SFD = "hD5".U

  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, 0.U )


  val bitCnt = Reg(UInt(3.W))
  val byteCnt = Reg(UInt(3.W)) //payload dont need to count

  val crcOut = crcUnit.io.crc
  val reset_crc = stateCurr === STATE_IDLE 
  crcUnit.reset := reset.asBool | reset_crc

  crcUnit.io.dataIn   := io.axis.bits.tdata
  crcUnit.io.isEnable := io.axis.fire

  val shiftData = RegInit(0.U(8.W))

  stateNext := Mux1H(Seq(
    (stateCurr === STATE_IDLE)     -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_PREAMBLE )),
    (stateCurr === STATE_PAYLOAD)  -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
    (stateCurr === STATE_FCS)      -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 7.U), STATE_IDLE, STATE_FCS )),
  ))

  io.serDat := shiftData.extract(7)
  io.axis.ready :=
    bitCnt === 7.U & (
      (stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
      (stateCurr === STATE_PAYLOAD)
    )



  when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
    shiftData := ETH_PRE
  } .otherwise{
    when( bitCnt =/= 7.U ){
      shiftData := shiftData << 1
    } .otherwise{ //bitCnt === 7.U
      when( stateCurr === STATE_PREAMBLE ){
        shiftData := MuxCase( ETH_PRE, Array(
          ( byteCnt === 6.U ) -> ETH_SFD,
          ( byteCnt === 7.U ) -> io.axis.bits.tdata,
        ))
      } .elsewhen( stateCurr === STATE_PAYLOAD ){
        shiftData := io.axis.bits.tdata
      } .elsewhen( stateCurr === STATE_FCS ){
        shiftData := PriorityMux(Seq(
          ( byteCnt === 0.U) -> ~crcOut( 7,0),
          ( byteCnt === 1.U) -> ~crcOut(15,8),
          ( byteCnt === 2.U) -> ~crcOut(23,16),
          ( byteCnt === 3.U) -> ~crcOut(31,24),
        ))
      }
    }
  }


  when( stateCurr === STATE_IDLE ){ //PRE
    bitCnt := 0.U
  } .otherwise{
    bitCnt := bitCnt + 1.U
  }

  when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
    byteCnt := 0.U
  } .elsewhen( bitCnt === 7.U ){
    byteCnt := byteCnt + 1.U
  }


}