package BACK

import chisel3._
import chisel3.util._


class ShareSRAMDP extends BlackBox with HasBlackBoxInline {

  class ShareSRAMDPIO extends Bundle{

      val addrA  = Input(UInt(15.W))
      val datawA  = Input( UInt(8.W) )
      val datarA  = Output( UInt(8.W) )
      val enwA    = Input(Bool())
      val enrA    = Input(Bool())
      val clockA  = Input(Bool())


      val addrB = Input(UInt(15.W))
      val datawB = Input( UInt(8.W) )
      val datarB = Output( UInt(8.W) )
      val enwB   = Input(Bool())
      val enrB   = Input(Bool())
      val clockB = Input(Bool())

  }
  val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO)

 setInline("ShareSRAMDP.v",
              """
      | module ShareSRAMDP(
      |  	input [7:0]  datawA,
      |  	input [14:0]   addrA,
      |  	input enwA,
      |  	input enrA,
      |  	output [7:0] datarA,
      |  	input clockA,
      |
      |  	input [7:0]  datawB,
      |  	input [14:0]   addrB,
      |  	input enwB,
      |  	input enrB,
      |  	output [7:0] datarB,
      |  	input clockB
      |  );
      |  
      |  reg [7:0] mem[0:32767];
      |  reg [7:0] data_outa_reg = 8'b0;
      |  reg [7:0] data_outb_reg = 8'b0;
      |
      |  assign datarA = data_outa_reg;
      |  assign datarB = data_outb_reg;
      |
      |  always@( posedge clockA ) begin
      |    if( enrA ) begin
      |    end
      |
      |    if( enwA ) begin
      |      mem[addrA] <= datawA;
      |    end else begin
      |      data_outa_reg <= mem[addrA];
      |    end
      |  end
      |
      |
      |  always@( posedge clockB ) begin
      |    if(enrB) begin
      |    end
      |
      |    if( enwB ) begin
      |      mem[addrB] <= datawB;
      |    end else begin
      |      data_outb_reg <= mem[addrB];
      |    end
      |  end
      |
      |  initial begin
      |     for( integer i = 0; i < 32768; i = i + 1 ) begin
      |       mem[i] = $random;
      |     end
      |  end
      |
      |
      |endmodule
    """.stripMargin)
}




class ShareSRAM2k extends BlackBox with HasBlackBoxInline {

  class ShareSRAM2kIO extends Bundle{
    val dataw = Input( UInt(8.W) )
    val addrw = Input(UInt(15.W))
    val enw   = Input(Bool())

    val datar = Output( UInt(8.W) )
    val addrr = Input(UInt(15.W))
    val enr   = Input(Bool())

    val clockr = Input(Bool())
    val clockw = Input(Bool())

  }
  val io: ShareSRAM2kIO = IO(new ShareSRAM2kIO)

 setInline("ShareSRAM2k.v",
              """

  | module ShareSRAM2k(
  |   	input [7:0] dataw,
  |   	input [14:0] addrw,
  |   	input enw,
  |   
  |   	output [7:0] datar,
  |   	input [14:0] addrr,
  |   	input enr,
  |   
  |   	input clockr,
  |     input clockw
  |   );
  |   
  |   	reg [7:0] ram[0:2047];
  |   	reg [7:0] data_r_reg;
  |   
  |   	always @(posedge clockw) begin
  |   		if(enw) begin
  |   			ram[addrw] <= #1 dataw;
  |   			end
  |     end
  |   
  |     always @(posedge clockr) begin
  |         if(enr) begin
  |              data_r_reg <= #1 ram[addrr];
  |         end
  |     end
  |   
  |   	assign datar = data_r_reg;
  |   
  |   initial begin
  |   	for ( integer i = 0; i < 2048; i = i + 1 ) begin
  |   		ram[i] = $random;
  |   	end
  |   
  |   	data_r_reg = $random;
  |   end
  |    
  | endmodule
    """.stripMargin)
}