package BACK

import chisel3._
import chisel3.util._


abstract class ShinSlvPhyBase extends Module{
  val downStreamCdrOut = Module(new CDROut)
  val downStreamCdrIn  = Module(new CDRIn )

  val upStreamCdrOut = Module(new CDROut)
  val upStreamCdrIn  = Module(new CDRIn )

  val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
  val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))

}

trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
  val headByte = Header_Info_Bundle.getWidth()/8
  require( headLen == 8 )

  val DownRecvStateIdle  = 0.U
  val DownRecvStateOHead = 1.U
  val DownRecvStateSData = 2.U
  val DownRecvStateFData = 3.U
  val DownRecvStateCRC   = 4.U

  val DownRecvStateIdle  = 0.U
  val DownRecvStateNHead = 1.U
  val DownRecvStateFData = 2.U

  val downOldHead = Reg( new Header_Info_Bundle )
  val downNewHead = Reg( new Header_Info_Bundle )

  val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )

  val downRecvSteteNext = Wire( UInt(3.W) )
  val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U )

  val downRecvCnt = Reg(UInt(10.W))

  val selfDataByte = Mux1H(Seq(
    downOldHead. ===     
  ))



  val forwardDataByte = downNewHead.length


  downRecvSteteNext := Mux1H(Seq(
    (downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ),
    (downRecvStateCurr === DownRecvStateOHead) -> Mux( downRecvCnt === ((headByte)-1).U & downStreamCdrIn.io.axis.fire, DownRecvStateSData, DownRecvStateOHead ),
    (downRecvStateCurr === DownRecvStateSData) -> Mux( downRecvCnt === (selfDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateFData, DownRecvStateSData),
    (downRecvStateCurr === DownRecvStateFData) -> Mux( downRecvCnt === (forwardDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateCRC, DownRecvStateFData),
    (downRecvStateCurr === DownRecvStateCRC  ) -> Mux( ~downStreamCdrIn.io.axis.valid, DownRecvStateIdle, DownRecvStateCRC ),
  ))

  when( downRecvStateCurr =/= downRecvSteteNext ){
    downRecvCnt := 0.U
  } .elsewhen( downStreamCdrIn.io.axis.fire ){
    downRecvCnt := downRecvCnt + 1.U
  }

//---------------

  when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){
    downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
  }


//---------------

  when( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData ){
    downNewHead.length   := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U )
    downNewHead.operator := downOldHead.operator
    downNewHead.param    := downOldHead.param
  }


  when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){
    downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata
  }

//---------------

  downStreamFifo.io.enq.valid :=
    downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid
  downStreamFifo.io.enq.bits  := downStreamCdrIn.io.axis.bits

  downStreamCdrIn.io.axis.ready := 
    (downRecvStateCurr === DownRecvStateOHead) |
    (downRecvStateCurr === DownRecvStateSData) |
    (downRecvStateCurr === DownRecvStateFData) |
    (downRecvStateCurr === DownRecvStateCRC  )

  assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )



  val downSendSteteNext = Wire( UInt(3.W) )
  val downSendStateCurr = RegNext( downSendSteteNext, 0.U )






  //got old header



  //create new header


  //got self data

  //forward downStream Data



  downStreamCdrIn.io.axis <> downStreamFifo.io.enq
  downStreamFifo.io.deq   <> downStreamCdrOut.io.axis
  assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )

}

trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
  val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )
  upStreamCdrIn.io.axis <> upStreamFifo.io.enq
  upStreamFifo.io.deq   <> upStreamCdrOut.io.axis
  assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )

}

// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyBase =>

// }


abstract class ShinSlvLinkBase extends ShinSlvPhyBase
with ShinSlvPhyDownStream
with ShinSlvPhyUpStream
// with ShinSlvPhyCloseLoop
{

}

trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>

}

trait ShinSlvLinkSync{ this: ShinSlvLinkBase =>

}

trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>

}

trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>

}

abstract class ShinSlvBase extends ShinSlvLinkBase
with ShinSlvLinkInit
with ShinSlvLinkSync
with ShinSlvLinkBCast
with ShinSlvLinkUCast