package BACK

import chisel3._
import chisel3.util._


class BackBoardSlvIO extends Bundle{
  val localHost = Input(UInt(6.W))

  val upStreamReqDat    = Input( Bool() )
  val downStreamReqDat  = Input( Bool() )

  val upStreamRespdat   = Output(Bool())
  val downStreamRespdat = Output(Bool())

  val refClk            = Input( Vec(4, Bool()) )
}


abstract class BackBoardSlvBase extends Module{
  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)


  val upStreamReq    = Module(new CDR4InBus)
  val downStreamReq  = Module(new CDR4InBus)

  val upStreamResp   = Module(new CDROutBus)
  val downStreamResp = Module(new CDROutBus)

  upStreamReq.io.refClk   := io.refClk
  downStreamReq.io.refClk := io.refClk
  upStreamReq.io.dat      := io.upStreamReqDat
  downStreamReq.io.dat    := io.downStreamReqDat

  io.upStreamRespdat   := upStreamResp.io.dat
  io.downStreamRespdat := downStreamResp.io.dat



  def IDLE            = 0.U
  def UPSTREAM_RESP   = 1.U
  def DOWNSTREAM_RESP = 2.U

  val stateNext = Wire( UInt(2.W) )
  val stateCurr = RegNext(stateNext, 0.U)

  stateNext := Mux1H(Seq(
    (stateCurr === IDLE)            -> Mux(upStreamReq.io.latDat.fire, Mux(upStreamReq.io.latDat.bits.address(5,1) === io.localHost, UPSTREAM_RESP, DOWNSTREAM_RESP), Mux(downStreamReq.io.latDat.fire, UPSTREAM_RESP, IDLE) ),
    (stateCurr === UPSTREAM_RESP)   -> Mux(upStreamResp.io.pkgDat.fire,   IDLE, UPSTREAM_RESP ),
    (stateCurr === DOWNSTREAM_RESP) -> Mux(downStreamResp.io.pkgDat.fire, IDLE, DOWNSTREAM_RESP ),
  ))

  val upStreamReqReady    = RegInit(false.B); upStreamReq.io.latDat.ready   := upStreamReqReady
  val downStreamReqReady  = RegInit(false.B); downStreamReq.io.latDat.ready := downStreamReqReady

  val upStreamRespValid   = RegInit(false.B); upStreamResp.io.pkgDat.valid := upStreamRespValid
  val upStreamRespInfo    = Reg(new CDRData); upStreamResp.io.pkgDat.bits  := upStreamRespInfo
  val downStreamRespValid = RegInit(false.B); downStreamResp.io.pkgDat.valid := downStreamRespValid
  val downStreamRespInfo  = Reg(new CDRData); downStreamResp.io.pkgDat.bits  := downStreamRespInfo

  val registersRD = Wire(UInt(32.W))



}

trait StatusControl{ this: BackBoardSlvBase =>

  when( upStreamResp.io.pkgDat.fire ){
    upStreamRespValid := false.B
  } .elsewhen( downStreamResp.io.pkgDat.fire ){
    downStreamRespValid := false.B
  }.elsewhen( upStreamReq.io.latDat.fire ){
    upStreamReqReady := false.B

    when( upStreamReq.io.latDat.bits.address(5,1) === io.localHost ){
      upStreamRespValid := true.B
      upStreamRespInfo.address  := upStreamReq.io.latDat.bits.address
      upStreamRespInfo.register := upStreamReq.io.latDat.bits.register
      upStreamRespInfo.data     := Mux(upStreamReq.io.latDat.bits.address.extract(0) === 0.U, registersRD, 0.U ) 
      upStreamRespInfo.hash     := 0.U

    } .otherwise{
      downStreamRespValid := true.B
      downStreamRespInfo  := upStreamReq.io.latDat.bits
    }

  } .elsewhen( downStreamReq.io.latDat.fire ){
    downStreamReqReady := false.B

    upStreamRespValid := true.B
    upStreamRespInfo  := downStreamReq.io.latDat.bits
  } .elsewhen( downStreamReq.io.latDat.valid & ~downStreamReq.io.latDat.ready && stateCurr === IDLE ){
    downStreamReqReady := true.B
  } .elsewhen( upStreamReq.io.latDat.valid & ~upStreamReq.io.latDat.ready & ~downStreamReq.io.latDat.valid & stateCurr === IDLE ){
    upStreamReqReady := true.B
  }



}


class BackBoardSlv extends BackBoardSlvBase with LocalRegisters