package BACK

import chisel3._
import chisel3.util._


class ShinTopIO extends Bundle{
  // val clk8x = Input(Bool())
  // val modeSel = Input(Bool())
	
  // val dDatIn   = Input(Bool())
  // val dDatOut  = Output(Bool())
  // val uDatIn   = Input(Bool())
  // val uDatOut  = Output(Bool())

  val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val downOut = Decoupled(new AXIS_Bundle(8))

  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val upOut = Decoupled(new AXIS_Bundle(8))

	// val qspi = 
	// val interrupt = Output(Bool())
	// val ctrl      = Input(UInt(4.W))

  val timeStamp = Input(UInt(64.W))

  val dSMdeq = Input( Vec(4, Bool()) )
  val uSMenq = Input( Vec(4, Bool()) )

  val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
  val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI


  val modeSel = Input(Bool())




  val req = Flipped(Valid(new Bundle{
    val txAddr    = UInt(15.W)
    val rxAddr    = UInt(15.W)
    val length  = UInt(12.W)
  }))
  val rsp = Valid(new Bundle{
    val isError = Bool()
    val length  = UInt(12.W)
  })
}



abstract class ShinTopBase extends Module{
  val io: ShinTopIO = IO(new ShinTopIO)

  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

	val slaveParser  = Module(new SlaveParser )
	val masterParser = Module(new MasterParser)


  val smUnit = Seq(
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
  )

  val sram = Seq(
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
  )




  smUnit(0).io.sram_r <> io.sram_r(0)
  smUnit(2).io.sram_r <> io.sram_r(1)
  smUnit(4).io.sram_r <> io.sram_r(2)
  smUnit(6).io.sram_r <> io.sram_r(3)



  smUnit(1).io.sram_w := io.sram_w(0)
  smUnit(3).io.sram_w := io.sram_w(1)
  smUnit(5).io.sram_w := io.sram_w(2)
  smUnit(7).io.sram_w := io.sram_w(3)


  smUnit(0).io.deq := io.dSMdeq(0)
  smUnit(2).io.deq := io.dSMdeq(1)
  smUnit(4).io.deq := io.dSMdeq(2)
  smUnit(6).io.deq := io.dSMdeq(3)


  smUnit(1).io.enq := io.uSMenq(0)
  smUnit(3).io.enq := io.uSMenq(1)
  smUnit(5).io.enq := io.uSMenq(2)
  smUnit(7).io.enq := io.uSMenq(3)








  for( i <- 0 until 4 ){
    for( j <- 0 until 4 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }
  }

  for( i <- 4 until 8 ){
    for( j <- 0 until 2 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }    
  }




  //default
  {
    smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)

    smUnit(1).io.sram_r.enr := false.B
    smUnit(3).io.sram_r.enr := false.B
    smUnit(5).io.sram_r.enr := false.B
    smUnit(7).io.sram_r.enr := false.B
    smUnit(1).io.sram_r.addrr := 0.U
    smUnit(3).io.sram_r.addrr := 0.U
    smUnit(5).io.sram_r.addrr := 0.U
    smUnit(7).io.sram_r.addrr := 0.U

    slaveParser.io.sram_r(0).datar := 0.U
    slaveParser.io.sram_r(1).datar := 0.U
    slaveParser.io.sram_r(2).datar := 0.U
    slaveParser.io.sram_r(3).datar := 0.U
    masterParser.io.sram_r.datar := 0.U

    smUnit(0).io.enq := false.B
    smUnit(2).io.enq := false.B
    smUnit(4).io.enq := false.B
    smUnit(6).io.enq := false.B

    smUnit(1).io.deq := false.B
    smUnit(3).io.deq := false.B
    smUnit(5).io.deq := false.B
    smUnit(7).io.deq := false.B


    io.downIn.ready := false.B
    slaveParser.io.downIn.valid := false.B
    slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.downOut.ready := false.B
    masterParser.io.downOut.ready := false.B
    io.downOut.valid := false.B
    io.downOut.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    io.upIn.ready := false.B
    slaveParser.io.upIn.valid := false.B
    slaveParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
    masterParser.io.upIn.valid := false.B
    masterParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.upOut.ready := false.B
    io.upOut.valid := false.B
    io.upOut.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
  }









}


trait ShinTopMaster{ this: ShinTopBase =>

  when(io.modeSel === true.B ){
    slaveParser.io.downOut <> io.downOut
    slaveParser.io.upIn    <> io.upIn 
  }

  when( io.modeSel === true.B ){
    smUnit(0).io.sram_w := masterParser.io.sram_w
    smUnit(1).io.sram_r <> masterParser.io.sram_r


    smUnit(0).io.enq := masterParser.io.rxEnq
    smUnit(1).io.deq := masterParser.io.txDeq

  }

  masterParser.io.req := io.req
  io.rsp := masterParser.io.rsp

  masterParser.io.trigAddr(0) := "hff".U
  masterParser.io.trigAddr(1) := "hff".U

  masterParser.io.timeStamp := io.timeStamp
}


trait ShinTopSlave{ this: ShinTopBase =>


  when( io.modeSel === false.B ){
    slaveParser.io.downIn  <> io.downIn
    slaveParser.io.downOut <> io.downOut
    slaveParser.io.upIn    <> io.upIn
    slaveParser.io.upOut   <> io.upOut
  }

  slaveParser.io.timeStamp := io.timeStamp


  slaveParser.io.trigAddr(0) := "hff".U
  slaveParser.io.trigAddr(1) := "hff".U
  slaveParser.io.trigAddr(2) := "hff".U
  slaveParser.io.trigAddr(3) := "hff".U
  slaveParser.io.trigAddr(4) := "hff".U
  slaveParser.io.trigAddr(5) := "hff".U
  slaveParser.io.trigAddr(6) := "hff".U
  slaveParser.io.trigAddr(7) := "hff".U





  when( io.modeSel === false.B ){
    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)

    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)

    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
    smUnit(6).io.enq := slaveParser.io.dSMenq(3)

    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)    
  }


  when(io.modeSel === false.B ){
    slaveParser.io.downIn  <> io.downIn
    slaveParser.io.downOut <> io.downOut
    slaveParser.io.upIn    <> io.upIn
    slaveParser.io.upOut   <> io.upOut    
  }


}






class ShinTop extends ShinTopBase
with ShinTopMaster
with ShinTopSlave