`timescale 1 ns / 1 ps





module ShinBack_tb();


    reg clock = 0;
    reg overClk = 0;
    reg reset = 1;

    reg  [15:0] io_FSMC_ADIn;
    wire [15:0] io_FSMC_ADOut;
    wire        io_FSMC_ADOEn;
    reg         io_FSMC_csn = 1;
    reg         io_FSMC_rdn = 1;
    reg         io_FSMC_wrn = 1;
    reg         io_FSMC_advn;


    reg         io_testIO = 0;

    wire [3:0] downStreamDat;
    wire [3:0] upStreamDat;


    ShinMst s_shinMst(
        .clock(clock),
        .reset(reset),

        .io_FSMC_ADIn(io_FSMC_ADIn),
        .io_FSMC_ADOut(io_FSMC_ADOut),
        .io_FSMC_ADOEn(io_FSMC_ADOEn),
        .io_FSMC_csn(io_FSMC_csn),
        .io_FSMC_rdn(io_FSMC_rdn),
        .io_FSMC_wrn(io_FSMC_wrn),
        .io_FSMC_advn(io_FSMC_advn),
        .io_interrupt(),
        .io_testIO(io_testIO),

        .io_serOut(downStreamDat[0]),
        .io_serIn(upStreamDat[0]),
        .io_overCLK(overClk)
    );

    ShinSlvBase s_ShinSlv0(
        .clock(clock),
        .reset(reset),
        .io_isOnline(),
        .io_isLast(1'b0),
        .io_DCIn(1'b0),
        .io_downSer_out(downStreamDat[1]),
        .io_downSer_in(downStreamDat[0]),
        .io_upSer_out(upStreamDat[0]),
        .io_upSer_in(upStreamDat[1]),
        .io_overCLK(overClk),
        .led()
    );

    ShinSlvBase s_ShinSlv1(
        .clock(clock),
        .reset(reset),
        .io_isOnline(),
        .io_isLast(1'b0),
        .io_DCIn(1'b0),
        .io_downSer_out(downStreamDat[2]),
        .io_downSer_in(downStreamDat[1]),
        .io_upSer_out(upStreamDat[1]),
        .io_upSer_in(upStreamDat[2]),
        .io_overCLK(overClk),
        .led()
    );

    ShinSlvBase s_ShinSlv2(
        .clock(clock),
        .reset(reset),
        .io_isOnline(),
        .io_isLast(1'b0),
        .io_DCIn(1'b0),
        .io_downSer_out(downStreamDat[3]),
        .io_downSer_in(downStreamDat[2]),
        .io_upSer_out(upStreamDat[2]),
        .io_upSer_in(upStreamDat[3]),
        .io_overCLK(overClk),
        .led()
    );

    ShinSlvBase s_ShinSlv3(
        .clock(clock),
        .reset(reset),
        .io_isOnline(),
        .io_isLast(1'b0),
        .io_DCIn(1'b0),
        .io_downSer_out(),
        .io_downSer_in(downStreamDat[3]),
        .io_upSer_out(upStreamDat[3]),
        .io_upSer_in(1'b0),
        .io_overCLK(overClk),
        .led()
    );




initial begin
    forever #80 clock = ~clock;
end

initial begin
    #10
    forever #20 overClk = ~overClk;
end

initial begin
    # 100 reset = 1;
    # 100 reset = 0;
end


initial begin

    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 1;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 1;
    io_testIO = 0;

    #5005


// @0 <- 512 length | operator
    #500
    io_FSMC_ADIn = 16'd0 | (1 << 11);
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 0;

    #500
    io_FSMC_ADIn = (16'd512 << 4) | 16'd0;
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 0;
    io_FSMC_advn = 1;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 1;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 1;

// @1 <- 0 param0
    #500
    io_FSMC_ADIn = 16'd1 | (1 << 11);
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 0;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 0;
    io_FSMC_advn = 1;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 1;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 1;

// @2 <- 0 param1
    #500
    io_FSMC_ADIn = 16'd2 | (1 << 11);
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 0;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 0;
    io_FSMC_advn = 1;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 1;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 1;

// @3 <- 0 param2
    #500
    io_FSMC_ADIn = 16'd3 | (1 << 11);
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 0;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 0;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 0;
    io_FSMC_advn = 1;

    #500
    io_FSMC_ADIn = 16'd0;
    io_FSMC_csn = 1;
    io_FSMC_rdn = 1;
    io_FSMC_wrn = 1;
    io_FSMC_advn = 1;


    #800
    io_testIO = 1;
    #160
    io_testIO = 0;
end



    initial begin
        # 10000000
        $finish;
    end

    initial begin
        $dumpfile("./build/wave.vcd"); //生成的vcd文件名称
        $dumpvars(0, ShinBack_tb);//tb模块名称
    end


endmodule