package BACK

import chisel3._
import chisel3.util._


trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>

  val inPin = Wire(UInt(16.W))


  val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
  val flitTrigger = Wire(Vec(9, Bool()))
  val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
  val digitalIn     = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }


  flitTrigger(0) := ~RegNext(flitTrigger(0))

  flitTrigger(1) := flitCnt(1) === 15.U
  when( ~RegNext(usTrigger) & usTrigger ){
    flitCnt(1) := flitCnt(1) + 1.U      
  }

  flitTrigger(2) := flitCnt(2)
  when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
    flitCnt(2) := ~flitCnt(2)
  }

  flitTrigger(3) := flitCnt(3)
  when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
    flitCnt(3) := ~flitCnt(3)
  }

  flitTrigger(4) := flitCnt(4)
  when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
    flitCnt(4) := ~flitCnt(4)
  }

  flitTrigger(5) := flitCnt(5)
  when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
    flitCnt(5) := ~flitCnt(5)
  }

  flitTrigger(6) := flitCnt(6)
  when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
    flitCnt(6) := ~flitCnt(6)
  }

  flitTrigger(7) := flitCnt(7)
  when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
    flitCnt(7) := ~flitCnt(7)
  }

  flitTrigger(8) := flitCnt(8)
  when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
    flitCnt(8) := ~flitCnt(8)
  }






  for( i <- 0 until 8 ) {
    for( j <- 0 until 2 ) {
      val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
      val flitHi  = RegInit(0.U((log2Ceil(16)).W))
      val shiftIn = RegNext( inPin(i+8*j) )

      val sample = 
        Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
          Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
            Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
              Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
                Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
                  Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
                    Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
                      Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
                      ))))))))


      when( sample ){
        flitter(0) := shiftIn
        (1 until 16).map{ k =>
          flitter(k) := flitter(k-1)
        }

        when( ~flitter(15) & flitter(0) ){
          flitHi := flitHi + 1.U
        } .elsewhen( flitter(15) & ~flitter(0) ){
          flitHi := flitHi - 1.U
        }

        when( flitHi === 12.U ){
          digitalIn(j)(i) := true.B
        } .elsewhen( flitHi === 3.U ){
          digitalIn(j)(i) := false.B
        }      

        // val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )

        // assert( flitHi <= 15.U )
        // assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )

      }
    }
  }

}




class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvIn16{
  
  val in = IO(Input(UInt(16.W)))

  inPin := in


  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
    digitalFilter(0) := downRegTemp(4)
    digitalFilter(1) := downRegTemp(5)
  }

  val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }

  when( statusPage === 0.U ){
    upReg(2) := digitalInSync(0)
    upReg(3) := digitalInSync(1)
    upReg(4) := digitalFilter(0)
    upReg(5) := digitalFilter(1)
  }

  page15reg2 := 0.U
  page15reg3 := 2.U
  page15reg4 := 2.U
  page15reg5 := 0.U
  page15reg6 := 0.U
  page15reg7 := 0.U
  page15reg8 := 0.U
  page15reg9 := 0.U
}