package BACK

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._


class SimpleSRAM()(implicit p: Parameters) extends BackModule{
  class SimpleSRAMIO extends Bundle{
    val mem = Flipped(new Mem_Port_Bundle)
  }

  val io: SimpleSRAMIO = IO(new SimpleSRAMIO)

  val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))


  io.mem.rdata := DontCare

  // when(io.mem.valid) {

    mem.write(
      io.mem.addr(11,2),
      VecInit( io.mem.wdata(31,24), io.mem.wdata(23,16), io.mem.wdata(15,8), io.mem.wdata(7,0) ),
      VecInit( io.mem.valid & io.mem.wstrb.extract(3), io.mem.valid & io.mem.wstrb.extract(2), io.mem.valid & io.mem.wstrb.extract(1), io.mem.valid & io.mem.wstrb.extract(0) )
    )


    io.mem.rdata := Cat( mem.read(io.mem.addr(11,2), true.B).reverse )



    // when ( io.mem.wstrb =/= 0.U ) {
    //   when(io.mem.wstrb.extract(0)) { mem(io.mem.addr(11,2))(0) := io.mem.wdata(7,0) }
    //   when(io.mem.wstrb.extract(1)) { mem(io.mem.addr(11,2))(1) := io.mem.wdata(15,8) }
    //   when(io.mem.wstrb.extract(2)) { mem(io.mem.addr(11,2))(2) := io.mem.wdata(23,16) }
    //   when(io.mem.wstrb.extract(3)) { mem(io.mem.addr(11,2))(3) := io.mem.wdata(31,24) }
    // } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
  // }

  val isReadAck = RegInit(false.B)
  when( io.mem.fire ){
    isReadAck := false.B
  } .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){
    isReadAck := true.B
  }

  io.mem.ready := 
    ( io.mem.wstrb =/= 0.U & true.B    ) |
    ( io.mem.wstrb === 0.U & isReadAck )




}