package BACK

import chisel3._
import chisel3.util._

class FSMC_Port_Bundle extends Bundle{

  val addr    = Input(UInt(12.W))
  val dataIn  = Input(UInt(8.W))
  val dataOut = Output(UInt(8.W))
  val dataOEn = Output(Bool())
  val cen     = Input(Bool())
  val oen     = Input(Bool())
  val wen     = Input(Bool())
}


class BackBoardMstIO extends Bundle{
  val FSMC = new FSMC_Port_Bundle

  val reset     = Input(Bool())
  val oser_pclk = Input(Bool())
  val oser_fclk = Input(Bool())
        val ides_pclk = Input(Bool())
  val ides_fclk = Input(Bool())

  val lvds_down_dout = Output(Bool())
  val lvds_up_din    = Input(Bool())
}


class BackBoardMstBase extends Module{
  val io: BackBoardMstIO = IO(new BackBoardMstIO)


  val fsmcSlv = Module(new FSMCSlv)

  fsmcSlv.io.FSMC <> io.FSMC


  val lvdsMst = Module(new Lvds_Bus_Master)



  val ( cnt, trigger ) = Counter(Range( 0,1023))






  val status  = RegInit(0.U(8.W))
  val slvNum  = RegInit(0.U(6.W))

  val mirror = Module(new MirrorSRAM)
  mirror.io.clock := io.ides_pclk.asBool
  mirror.io.reset := io.reset.asBool

}





trait BackBoardMstFSMC{ this: BackBoardMstBase =>

  val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
  val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
  val fsmcCEnSync    = ShiftRegister( io.FSMC.cen,    2, true.B, true.B )
  val fsmcOEnSync    = ShiftRegister( io.FSMC.oen,    2, true.B, true.B )
  val fsmcWEnSync    = ShiftRegister( io.FSMC.wen,    2, true.B, true.B )

  io.FSMC.dataOEn := io.FSMC.oen


  io.FSMC.dataOut   := mirror.io.datar_a
  mirror.io.ce_a    := (~fsmcCEnSync & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync | ~fsmcWEnSync) )
  mirror.io.we_a    := ~fsmcWEnSync
  mirror.io.addr_a  := fsmcAddrSync(10,0)
  mirror.io.dataw_a := fsmcdataInSync

}

trait BackBoardMstLVDS{ this: BackBoardMstBase =>
  lvdsMst.io.rst_n     := ~io.reset
  lvdsMst.io.oser_pclk := io.oser_pclk
  lvdsMst.io.oser_fclk := io.oser_fclk
  lvdsMst.io.ides_pclk := io.ides_pclk
  lvdsMst.io.ides_fclk := io.ides_fclk
  
  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
  lvdsMst.io.lvds_up_din := io.lvds_up_din
    
  
  lvdsMst.io.tx_start := false.B

  
  .elsewhen( cnt === 0.U ){
    
  } .elsewhen( cnt === 1.U ){
    lvdsMst.io.tx_start := true.B
  }


  lvdsMst.io.frame_info_update_en := (cnt === 0.U)
  lvdsMst.io.slave_type_num       := Cat( "b00".U(2.W), slvNum )
  lvdsMst.io.slave_data_length    := (8/8*4*8-1).U


  lvdsMst.io.tx_start             = Input(Bool())
  lvdsMst.io.tx_data_in           = Input(UInt(8.W))
  lvdsMst.io.tx_data_ready        = Output(Bool())
  lvdsMst.io.downstream_busy      = Output(Bool())

  lvdsMst.io.rx_data_out          = Output(UInt(8.W))
  lvdsMst.io.rx_data_valid        = Output(Bool())

  lvdsMst.io.upstream_crc_valid     = Output(Bool())
  lvdsMst.io.upstream_crc_err       = Output(Bool())
  lvdsMst.io.upstream_crc_err_count = Output(UInt(8.W))
  lvdsMst.io.upstream_cdr_err       = Output(Bool())
}