package BACK import chisel3._ import chisel3.util._ class AXIS_Bundle(dw: Int) extends Bundle{ val tdata = UInt(dw.W) val tlast = Bool() val tuser = Bool() } //work in 100MHZ class CDROutIO extends Bundle{ val axis = Flipped(Decoupled(new AXIS_Bundle(8))) val serDat = Output(Bool()) val flush = Input(Bool()) } class CDROut extends Module with RequireAsyncReset{ val io: CDROutIO = IO(new CDROutIO) def PRE_NUM = 3 //PRE_NUM should >= 3 def STATE_IDLE = 0.U def STATE_PREAMBLE = 1.U def STATE_PAYLOAD = 2.U val ETH_PRE = "b1100010001".U(10.W) val ETH_SFD = "b0110100111".U(10.W) val stateNext = Wire(UInt(2.W)) val stateCurr = RegNext( stateNext, 0.U ) val bitCnt = Reg(UInt(4.W)) val byteCnt = Reg(UInt(3.W)) //payload dont need to count val shiftData = RegInit(0.U(10.W)) stateNext := Mux( io.flush, STATE_IDLE, Mux1H(Seq( (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )), (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ), )) ) io.serDat := shiftData.extract(9) io.axis.ready := bitCnt === 9.U & ( (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | (stateCurr === STATE_PAYLOAD) ) // assert( ~(~io.axis.valid & io.axis.ready) ) when( ~io.axis.valid & io.axis.ready ){ printf( "Error, CDROut axis overflow!\n" ) } when( io.flush ){ shiftData := 0.U } .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE shiftData := ETH_PRE } .otherwise{ when( bitCnt =/= 9.U ){ shiftData := shiftData << 1 } .otherwise{ //bitCnt === 9.U when( stateCurr === STATE_PREAMBLE ){ shiftData := MuxCase( ETH_PRE, Array( ( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD, ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata), )) } .elsewhen( stateCurr === STATE_PAYLOAD ){ shiftData := Dualb4b5Encoder(io.axis.bits.tdata) } } } when( stateCurr === STATE_IDLE ){ //PRE bitCnt := 0.U } .otherwise{ when( bitCnt === 9.U ){ bitCnt := 0.U } .otherwise{ bitCnt := bitCnt + 1.U } } when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ byteCnt := 0.U } .elsewhen( bitCnt === 9.U ){ byteCnt := byteCnt + 1.U } }