package BACK

import chisel3._
import chisel3.util._


class BackBoardMstIO extends Bundle{
  val downStreamReqDat  = Input( Bool() )
  val downStreamRespdat = Output(Bool())

  val CS   = Input(Bool())
  val MISO = Output(Bool())
  val MOSI = Input(Bool())
  val SCK  = Input(Bool())

  val interrupt = Output(Bool())

  val clk4            = Input( Bool() )

}


class BackBoardMst extends Module{
  val io: BackBoardMstIO = IO(new BackBoardMstIO)


  
}