circuit MIIM : module MIIM : input clock : Clock input reset : UInt<1> output io : { flip mdi : UInt<1>, mdc : UInt<1>, mdo : UInt<1>, mdoEn : UInt<1>, flip Divider : UInt<8>, flip NoPre : UInt<1>, flip WCtrlData : UInt<1>, flip CtrlData : UInt<16>, flip Fiad : UInt<5>, flip Rgad : UInt<5>, flip RStat : UInt<1>, flip ScanStat : UInt<1>, Busy : UInt<1>, LinkFail : UInt<1>, Nvalid : UInt<1>, Prsd : UInt<16>, WCtrlDataStart : UInt<1>, RStatStart : UInt<1>, UpdateMIIRX_DATAReg : UInt<1>} wire ByteSelect : UInt<1>[4] @[MII.scala 42:24] reg Counter : UInt<8>, clock with : reset => (reset, UInt<8>("h1")) @[MII.scala 46:25] reg mdc : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 47:20] node _mdcEn_T = eq(Counter, UInt<1>("h0")) @[MII.scala 48:27] node _mdcEn_T_1 = not(mdc) @[MII.scala 48:38] node mdcEn = and(_mdcEn_T, _mdcEn_T_1) @[MII.scala 48:36] node _mdcEn_n_T = eq(Counter, UInt<1>("h0")) @[MII.scala 49:27] node mdcEn_n = and(_mdcEn_n_T, mdc) @[MII.scala 49:36] reg ShiftReg : UInt<8>, clock with : reset => (reset, UInt<8>("h0")) @[MII.scala 51:25] reg Prsd : UInt<16>, clock with : reset => (reset, UInt<16>("h0")) @[MII.scala 52:25] reg LinkFail : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 53:25] reg BitCounter : UInt<7>, clock with : reset => (reset, UInt<7>("h0")) @[MII.scala 56:27] node EndOp = eq(BitCounter, UInt<6>("h3f")) @[MII.scala 57:26] reg InProgress : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 60:27] reg InProgress_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] InProgress_q_0 <= InProgress @[Reg.scala 36:22] reg InProgress_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] InProgress_q_1 <= InProgress_q_0 @[Reg.scala 36:22] reg InProgress_q_2 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] InProgress_q_2 <= InProgress_q_1 @[Reg.scala 36:22] node _EndBusy_T = not(InProgress_q_1) @[MII.scala 62:32] node _EndBusy_T_1 = and(_EndBusy_T, InProgress_q_2) @[MII.scala 62:49] reg EndBusy_r : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] EndBusy_r <= _EndBusy_T_1 @[Reg.scala 36:22] reg EndBusy : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] EndBusy <= EndBusy_r @[Reg.scala 36:22] reg WriteOp : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 64:27] io.mdc <= mdc @[MII.scala 69:10] io.LinkFail <= LinkFail @[MII.scala 70:15] io.Prsd <= Prsd @[MII.scala 71:11] node _TempDivider_T = lt(io.Divider, UInt<2>("h2")) @[MII.scala 82:39] node TempDivider = mux(_TempDivider_T, UInt<2>("h2"), io.Divider) @[MII.scala 82:26] node _CounterPreset_T = shr(TempDivider, 1) @[MII.scala 83:37] node _CounterPreset_T_1 = sub(_CounterPreset_T, UInt<1>("h1")) @[MII.scala 83:44] node CounterPreset = tail(_CounterPreset_T_1, 1) @[MII.scala 83:44] node _T = eq(Counter, UInt<1>("h0")) @[MII.scala 85:17] when _T : @[MII.scala 85:27] node _mdc_T = not(mdc) @[MII.scala 86:12] mdc <= _mdc_T @[MII.scala 86:9] Counter <= CounterPreset @[MII.scala 87:13] else : node _Counter_T = sub(Counter, UInt<1>("h1")) @[MII.scala 89:24] node _Counter_T_1 = tail(_Counter_T, 1) @[MII.scala 89:24] Counter <= _Counter_T_1 @[MII.scala 89:13] node _LatchByte0_T = not(WriteOp) @[MII.scala 97:47] node _LatchByte0_T_1 = and(InProgress, _LatchByte0_T) @[MII.scala 97:45] node _LatchByte0_T_2 = eq(BitCounter, UInt<6>("h3f")) @[MII.scala 97:69] node _LatchByte0_T_3 = and(_LatchByte0_T_1, _LatchByte0_T_2) @[MII.scala 97:56] reg LatchByte0_r : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] LatchByte0_r <= _LatchByte0_T_3 @[Reg.scala 36:22] reg LatchByte0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] LatchByte0 <= LatchByte0_r @[Reg.scala 36:22] node _LatchByte1_T = not(WriteOp) @[MII.scala 98:47] node _LatchByte1_T_1 = and(InProgress, _LatchByte1_T) @[MII.scala 98:45] node _LatchByte1_T_2 = eq(BitCounter, UInt<6>("h37")) @[MII.scala 98:69] node _LatchByte1_T_3 = and(_LatchByte1_T_1, _LatchByte1_T_2) @[MII.scala 98:56] reg LatchByte1_r : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] LatchByte1_r <= _LatchByte1_T_3 @[Reg.scala 36:22] reg LatchByte1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] LatchByte1 <= LatchByte1_r @[Reg.scala 36:22] node _ByteSelect_0_T = eq(BitCounter, UInt<1>("h0")) @[MII.scala 100:58] node _ByteSelect_0_T_1 = and(io.NoPre, _ByteSelect_0_T) @[MII.scala 100:44] node _ByteSelect_0_T_2 = not(io.NoPre) @[MII.scala 100:71] node _ByteSelect_0_T_3 = eq(BitCounter, UInt<6>("h20")) @[MII.scala 100:95] node _ByteSelect_0_T_4 = and(_ByteSelect_0_T_2, _ByteSelect_0_T_3) @[MII.scala 100:81] node _ByteSelect_0_T_5 = or(_ByteSelect_0_T_1, _ByteSelect_0_T_4) @[MII.scala 100:68] node _ByteSelect_0_T_6 = and(InProgress, _ByteSelect_0_T_5) @[MII.scala 100:31] ByteSelect[0] <= _ByteSelect_0_T_6 @[MII.scala 100:17] node _ByteSelect_1_T = eq(BitCounter, UInt<6>("h28")) @[MII.scala 101:45] node _ByteSelect_1_T_1 = and(InProgress, _ByteSelect_1_T) @[MII.scala 101:31] ByteSelect[1] <= _ByteSelect_1_T_1 @[MII.scala 101:17] node _ByteSelect_2_T = and(InProgress, WriteOp) @[MII.scala 102:31] node _ByteSelect_2_T_1 = eq(BitCounter, UInt<6>("h30")) @[MII.scala 102:55] node _ByteSelect_2_T_2 = and(_ByteSelect_2_T, _ByteSelect_2_T_1) @[MII.scala 102:41] ByteSelect[2] <= _ByteSelect_2_T_2 @[MII.scala 102:17] node _ByteSelect_3_T = and(InProgress, WriteOp) @[MII.scala 103:31] node _ByteSelect_3_T_1 = eq(BitCounter, UInt<6>("h38")) @[MII.scala 103:55] node _ByteSelect_3_T_2 = and(_ByteSelect_3_T, _ByteSelect_3_T_1) @[MII.scala 103:41] ByteSelect[3] <= _ByteSelect_3_T_2 @[MII.scala 103:17] when mdcEn_n : @[MII.scala 105:16] node _T_1 = or(ByteSelect[0], ByteSelect[1]) @[MII.scala 106:29] node _T_2 = or(_T_1, ByteSelect[2]) @[MII.scala 106:29] node _T_3 = or(_T_2, ByteSelect[3]) @[MII.scala 106:29] when _T_3 : @[MII.scala 106:34] node _ShiftReg_T = not(WriteOp) @[MII.scala 108:44] node _ShiftReg_T_1 = bits(io.Fiad, 4, 1) @[MII.scala 108:70] node ShiftReg_lo = cat(WriteOp, _ShiftReg_T_1) @[Cat.scala 33:92] node ShiftReg_hi = cat(UInt<2>("h1"), _ShiftReg_T) @[Cat.scala 33:92] node _ShiftReg_T_2 = cat(ShiftReg_hi, ShiftReg_lo) @[Cat.scala 33:92] node _ShiftReg_T_3 = bits(io.Fiad, 0, 0) @[MII.scala 109:45] node _ShiftReg_T_4 = bits(io.Rgad, 4, 0) @[MII.scala 109:57] node ShiftReg_hi_1 = cat(_ShiftReg_T_3, _ShiftReg_T_4) @[Cat.scala 33:92] node _ShiftReg_T_5 = cat(ShiftReg_hi_1, UInt<2>("h2")) @[Cat.scala 33:92] node _ShiftReg_T_6 = bits(io.CtrlData, 15, 8) @[MII.scala 110:37] node _ShiftReg_T_7 = bits(io.CtrlData, 7, 0) @[MII.scala 111:37] node _ShiftReg_T_8 = mux(ByteSelect[0], _ShiftReg_T_2, UInt<1>("h0")) @[Mux.scala 27:73] node _ShiftReg_T_9 = mux(ByteSelect[1], _ShiftReg_T_5, UInt<1>("h0")) @[Mux.scala 27:73] node _ShiftReg_T_10 = mux(ByteSelect[2], _ShiftReg_T_6, UInt<1>("h0")) @[Mux.scala 27:73] node _ShiftReg_T_11 = mux(ByteSelect[3], _ShiftReg_T_7, UInt<1>("h0")) @[Mux.scala 27:73] node _ShiftReg_T_12 = or(_ShiftReg_T_8, _ShiftReg_T_9) @[Mux.scala 27:73] node _ShiftReg_T_13 = or(_ShiftReg_T_12, _ShiftReg_T_10) @[Mux.scala 27:73] node _ShiftReg_T_14 = or(_ShiftReg_T_13, _ShiftReg_T_11) @[Mux.scala 27:73] wire _ShiftReg_WIRE : UInt<8> @[Mux.scala 27:73] _ShiftReg_WIRE <= _ShiftReg_T_14 @[Mux.scala 27:73] ShiftReg <= _ShiftReg_WIRE @[MII.scala 107:16] else : node _ShiftReg_T_15 = bits(ShiftReg, 6, 0) @[MII.scala 114:31] node _ShiftReg_T_16 = cat(_ShiftReg_T_15, io.mdi) @[Cat.scala 33:92] ShiftReg <= _ShiftReg_T_16 @[MII.scala 114:16] when LatchByte0 : @[MII.scala 115:23] node _Prsd_T = bits(Prsd, 15, 8) @[MII.scala 116:25] node _Prsd_T_1 = bits(ShiftReg, 6, 0) @[MII.scala 116:41] node Prsd_hi = cat(_Prsd_T, _Prsd_T_1) @[Cat.scala 33:92] node _Prsd_T_2 = cat(Prsd_hi, io.mdi) @[Cat.scala 33:92] Prsd <= _Prsd_T_2 @[MII.scala 116:14] node _T_4 = eq(io.Rgad, UInt<1>("h1")) @[MII.scala 117:22] when _T_4 : @[MII.scala 117:30] node _LinkFail_T = bits(ShiftReg, 1, 1) @[MII.scala 118:40] node _LinkFail_T_1 = not(_LinkFail_T) @[MII.scala 118:23] LinkFail <= _LinkFail_T_1 @[MII.scala 118:20] else : when LatchByte1 : @[MII.scala 120:30] node _Prsd_T_3 = bits(ShiftReg, 6, 0) @[MII.scala 121:29] node _Prsd_T_4 = bits(Prsd, 7, 0) @[MII.scala 121:48] node Prsd_hi_1 = cat(_Prsd_T_3, io.mdi) @[Cat.scala 33:92] node _Prsd_T_5 = cat(Prsd_hi_1, _Prsd_T_4) @[Cat.scala 33:92] Prsd <= _Prsd_T_5 @[MII.scala 121:14] node _SerialEn_T = and(WriteOp, InProgress) @[MII.scala 131:29] node _SerialEn_T_1 = gt(BitCounter, UInt<5>("h1f")) @[MII.scala 131:57] node _SerialEn_T_2 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 131:81] node _SerialEn_T_3 = and(_SerialEn_T_2, io.NoPre) @[MII.scala 131:91] node _SerialEn_T_4 = or(_SerialEn_T_1, _SerialEn_T_3) @[MII.scala 131:64] node _SerialEn_T_5 = and(_SerialEn_T, _SerialEn_T_4) @[MII.scala 131:42] node _SerialEn_T_6 = not(WriteOp) @[MII.scala 132:20] node _SerialEn_T_7 = and(_SerialEn_T_6, InProgress) @[MII.scala 132:29] node _SerialEn_T_8 = gt(BitCounter, UInt<5>("h1f")) @[MII.scala 132:58] node _SerialEn_T_9 = lt(BitCounter, UInt<6>("h2e")) @[MII.scala 132:78] node _SerialEn_T_10 = and(_SerialEn_T_8, _SerialEn_T_9) @[MII.scala 132:65] node _SerialEn_T_11 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 132:104] node _SerialEn_T_12 = and(_SerialEn_T_11, io.NoPre) @[MII.scala 132:114] node _SerialEn_T_13 = or(_SerialEn_T_10, _SerialEn_T_12) @[MII.scala 132:87] node _SerialEn_T_14 = and(_SerialEn_T_7, _SerialEn_T_13) @[MII.scala 132:42] node SerialEn = or(_SerialEn_T_5, _SerialEn_T_14) @[MII.scala 131:107] node _mdoEn_T = lt(BitCounter, UInt<6>("h20")) @[MII.scala 134:66] node _mdoEn_T_1 = and(InProgress, _mdoEn_T) @[MII.scala 134:54] node _mdoEn_T_2 = or(SerialEn, _mdoEn_T_1) @[MII.scala 134:40] reg mdoEn_r : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdoEn_r <= _mdoEn_T_2 @[Reg.scala 36:22] reg mdoEn_r_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdoEn_r_1 <= mdoEn_r @[Reg.scala 36:22] reg mdoEn : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdoEn <= mdoEn_r_1 @[Reg.scala 36:22] node _mdo_2d_T = not(SerialEn) @[MII.scala 135:27] node _mdo_2d_T_1 = lt(BitCounter, UInt<6>("h20")) @[MII.scala 135:49] node _mdo_2d_T_2 = and(_mdo_2d_T, _mdo_2d_T_1) @[MII.scala 135:37] reg mdo_2d : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdo_2d <= _mdo_2d_T_2 @[Reg.scala 36:22] node _mdo_d_T = bits(ShiftReg, 7, 7) @[MII.scala 136:43] node _mdo_d_T_1 = or(_mdo_d_T, mdo_2d) @[MII.scala 136:47] reg mdo_d : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdo_d <= _mdo_d_T_1 @[Reg.scala 36:22] reg mdo : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn_n : @[Reg.scala 36:18] mdo <= mdo_d @[Reg.scala 36:22] io.mdo <= mdo @[MII.scala 138:10] io.mdoEn <= mdoEn @[MII.scala 139:12] reg WCtrlData_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] WCtrlData_q_0 <= io.WCtrlData @[Reg.scala 36:22] reg WCtrlData_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] WCtrlData_q_1 <= WCtrlData_q_0 @[Reg.scala 36:22] reg WCtrlData_q_2 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] WCtrlData_q_2 <= WCtrlData_q_1 @[Reg.scala 36:22] reg WCtrlDataStart : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 147:31] reg WCtrlDataStart_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] WCtrlDataStart_q_0 <= WCtrlDataStart @[Reg.scala 36:22] reg WCtrlDataStart_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] WCtrlDataStart_q_1 <= WCtrlDataStart_q_0 @[Reg.scala 36:22] node _WriteDataOp_T = not(WCtrlDataStart_q_1) @[MII.scala 149:44] node WriteDataOp = and(WCtrlDataStart_q_0, _WriteDataOp_T) @[MII.scala 149:42] io.WCtrlDataStart <= WCtrlDataStart @[MII.scala 150:21] wire StartOp : UInt<1> @[MII.scala 156:21] when EndBusy : @[MII.scala 160:18] WCtrlDataStart <= UInt<1>("h0") @[MII.scala 161:20] else : node _T_5 = not(WCtrlData_q_2) @[MII.scala 162:33] node _T_6 = and(WCtrlData_q_1, _T_5) @[MII.scala 162:31] when _T_6 : @[MII.scala 162:50] WCtrlDataStart <= UInt<1>("h1") @[MII.scala 163:20] node _WCtrlDataStart_q0_T = not(EndBusy) @[MII.scala 167:62] reg WCtrlDataStart_q0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when _WCtrlDataStart_q0_T : @[Reg.scala 36:18] WCtrlDataStart_q0 <= WCtrlDataStart @[Reg.scala 36:22] node _UpdateMIIRX_DATAReg_T = not(WCtrlDataStart_q0) @[MII.scala 168:47] node _UpdateMIIRX_DATAReg_T_1 = and(EndBusy, _UpdateMIIRX_DATAReg_T) @[MII.scala 168:45] reg UpdateMIIRX_DATAReg : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 168:36] UpdateMIIRX_DATAReg <= _UpdateMIIRX_DATAReg_T_1 @[MII.scala 168:36] io.UpdateMIIRX_DATAReg <= UpdateMIIRX_DATAReg @[MII.scala 169:26] reg RStat_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] RStat_q_0 <= io.RStat @[Reg.scala 36:22] reg RStat_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] RStat_q_1 <= RStat_q_0 @[Reg.scala 36:22] reg RStat_q_2 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] RStat_q_2 <= RStat_q_1 @[Reg.scala 36:22] reg RStatStart : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 174:27] reg RStatStart_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] RStatStart_q_0 <= RStatStart @[Reg.scala 36:22] reg RStatStart_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] RStatStart_q_1 <= RStatStart_q_0 @[Reg.scala 36:22] node _ReadStatusOp_T = not(RStatStart_q_1) @[MII.scala 176:44] node ReadStatusOp = and(RStatStart_q_0, _ReadStatusOp_T) @[MII.scala 176:42] io.RStatStart <= RStatStart @[MII.scala 177:17] when EndBusy : @[MII.scala 179:18] RStatStart <= UInt<1>("h0") @[MII.scala 180:16] else : node _T_7 = not(RStat_q_2) @[MII.scala 181:28] node _T_8 = and(RStat_q_1, _T_7) @[MII.scala 181:26] when _T_8 : @[MII.scala 181:40] RStatStart <= UInt<1>("h1") @[MII.scala 182:16] when mdcEn : @[MII.scala 188:14] when StartOp : @[MII.scala 189:19] InProgress <= UInt<1>("h1") @[MII.scala 190:18] else : when EndOp : @[MII.scala 191:24] InProgress <= UInt<1>("h0") @[MII.scala 192:18] reg ScanStat_q_0 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] ScanStat_q_0 <= io.ScanStat @[Reg.scala 36:22] reg ScanStat_q_1 : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when UInt<1>("h1") : @[Reg.scala 36:18] ScanStat_q_1 <= ScanStat_q_0 @[Reg.scala 36:22] reg SyncStatmdcEn : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[Reg.scala 35:20] when mdcEn : @[Reg.scala 36:18] SyncStatmdcEn <= ScanStat_q_1 @[Reg.scala 36:22] node _ScanStatusOp_T = not(InProgress) @[MII.scala 200:44] node _ScanStatusOp_T_1 = and(SyncStatmdcEn, _ScanStatusOp_T) @[MII.scala 200:42] node _ScanStatusOp_T_2 = not(InProgress_q_0) @[MII.scala 200:58] node _ScanStatusOp_T_3 = and(_ScanStatusOp_T_1, _ScanStatusOp_T_2) @[MII.scala 200:56] node _ScanStatusOp_T_4 = not(InProgress_q_1) @[MII.scala 200:77] node ScanStatusOp = and(_ScanStatusOp_T_3, _ScanStatusOp_T_4) @[MII.scala 200:75] reg Nvalid : UInt<1>, clock with : reset => (reset, UInt<1>("h0")) @[MII.scala 203:23] io.Nvalid <= Nvalid @[MII.scala 204:13] node _T_9 = not(InProgress_q_1) @[MII.scala 206:9] node _T_10 = and(_T_9, InProgress_q_2) @[MII.scala 206:26] when _T_10 : @[MII.scala 206:46] Nvalid <= UInt<1>("h0") @[MII.scala 207:12] else : node _T_11 = not(SyncStatmdcEn) @[MII.scala 208:32] node _T_12 = and(ScanStat_q_1, _T_11) @[MII.scala 208:30] when _T_12 : @[MII.scala 208:48] Nvalid <= UInt<1>("h1") @[MII.scala 209:12] when mdcEn : @[MII.scala 215:14] when StartOp : @[MII.scala 216:19] node _T_13 = not(InProgress) @[MII.scala 217:13] when _T_13 : @[MII.scala 217:26] node _WriteOp_T = mux(WriteDataOp, UInt<1>("h1"), UInt<1>("h0")) @[MII.scala 218:23] WriteOp <= _WriteOp_T @[MII.scala 218:17] else : when EndOp : @[MII.scala 220:24] WriteOp <= UInt<1>("h0") @[MII.scala 221:15] when mdcEn : @[MII.scala 226:16] when InProgress : @[MII.scala 227:24] node _T_14 = eq(BitCounter, UInt<1>("h0")) @[MII.scala 228:35] node _T_15 = and(io.NoPre, _T_14) @[MII.scala 228:22] when _T_15 : @[MII.scala 228:45] BitCounter <= UInt<6>("h21") @[MII.scala 229:20] else : node _BitCounter_T = add(BitCounter, UInt<1>("h1")) @[MII.scala 231:34] node _BitCounter_T_1 = tail(_BitCounter_T, 1) @[MII.scala 231:34] BitCounter <= _BitCounter_T_1 @[MII.scala 231:20] else : BitCounter <= UInt<1>("h0") @[MII.scala 234:18] node _StartOp_T = or(WriteDataOp, ReadStatusOp) @[MII.scala 239:26] node _StartOp_T_1 = or(_StartOp_T, ScanStatusOp) @[MII.scala 239:41] StartOp <= _StartOp_T_1 @[MII.scala 239:11] node _io_Busy_T = or(io.WCtrlData, WCtrlDataStart) @[MII.scala 240:27] node _io_Busy_T_1 = or(_io_Busy_T, io.RStat) @[MII.scala 240:44] node _io_Busy_T_2 = or(_io_Busy_T_1, RStatStart) @[MII.scala 240:55] node _io_Busy_T_3 = or(_io_Busy_T_2, SyncStatmdcEn) @[MII.scala 240:68] node _io_Busy_T_4 = or(_io_Busy_T_3, EndBusy) @[MII.scala 240:84] node _io_Busy_T_5 = or(_io_Busy_T_4, InProgress) @[MII.scala 240:94] node _io_Busy_T_6 = or(_io_Busy_T_5, InProgress_q_2) @[MII.scala 240:107] node _io_Busy_T_7 = or(_io_Busy_T_6, Nvalid) @[MII.scala 240:125] io.Busy <= _io_Busy_T_7 @[MII.scala 240:11]