package BACK

import chisel3._
import chisel3.util._

class CommonRegisterBundle extends Bundle{
  val isMstNSlv = Bool()
  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(16.W)

  val spiSel       = UInt(2.W)

  val isSoftReset  = Bool()
  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  val upRecErrorCnt   = UInt(32.W)
  val downRecErrorCnt = UInt(32.W)
  val upForwardErrorCnt   = UInt(32.W)
  val downForwardErrorCnt = UInt(32.W)

  val qspiErrorCnt   = UInt(32.W)
  val forwardCnt     = UInt(32.W)
  val recByteCnt     = UInt(32.W)
  val forwardByteCnt = UInt(32.W)


  val wdtStatus   = UInt(16.W)
  val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val deltaTime = UInt(32.W)

  val linkStatus = UInt(8.W)

}

class MasterRegisterBundle extends Bundle{

  val isExInfoInit = Bool()
  val isTxReq      = UInt(8.W)
  val txStatus     = UInt(16.W)


  val intEnable    = UInt(8.W)
  val intMask      = UInt(8.W)
  val intStatus    = UInt(8.W)

}


class SlaveRegisterBundle extends Bundle{

  val RAMSize   = UInt(8.W)
  val MMUNum    = UInt(8.W)

  val nodeSeqAddr = UInt(16.W)
  val nodeSetAddr = UInt(16.W)


  val ebmmu = Vec(8, new Bundle{
    val logicAddr = UInt(32.W)
    val length = UInt(16.W)
    val phyAddr = UInt(32.W)
    val op = UInt(2.W)
    val enable = Bool()
  })

  val intStatus = UInt(16.W)
  val mb = Vec(8, new Bundle{
    val ctrl = UInt(8.W)
    val status = UInt(8.W)
  })


  val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
  val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
  val mstTimeStamp  = UInt(64.W) //主站时间戳

  val dcSyncEnable = Bool()
  val dcSyncWidth  = UInt(16.W)
}



class InterfaceIO extends Bundle{
  val ospi = new SPIInterfaceIO

  // val req = Valid(new Bundle{
  //   val addr = UInt(16.W)
  //   val dataw = UInt(8.W)
  //   val isWRn = Bool()
  // })

  // val resp = Valid(new Bundle{
  //   datar = UInt(8.W)
  // })
}


abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)

  val oSpi = Module(new SpiInterface)
  io.ospi <> oSpi.io.spi


  val cReg = Wire(new CommonRegisterBundle)
  val mReg = Wire(new MasterRegisterBundle)
  val sReg = Wire(new SlaveRegisterBundle)

  def AcquireReg(addr: UInt): UInt = {
    Mux1H(Seq(

    ))
  }

  def UpdateReg( addr: UInt ) = {
    
  }


}

trait InterfaceMCUop{ this: InterfaceBase =>



  oSpi.io.addrSel = Output(UInt(16.W))
  oSpi.io.dataw   = Output( UInt(8.W) )
  oSpi.io.datar   := RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR )
  oSpi.io.isEnW   = Output(Bool())
  
}

trait InterfaceCheckSM{ this: InterfaceBase =>
  when( oSpi.io.isEnR & oSpi.io.addrSel ===  ){

  }
}

trait InterfaceLVDSop{ this: InterfaceBase =>

}



class Interface extends InterfaceBase
with InterfaceMCUop
{

}