package BACK

import chisel3._
import chisel3.util._


//work in 100MHZ
class CDRInIO extends Bundle{
  val axis = Decoupled(new AXIS_Bundle(8))
  val serDat = Input(Bool())

}


abstract class CDRInBase extends Module{


  val io: CDRInIO = IO(new CDRInIO)


  val syncSerDat = Wire(Bool())
}

trait CDRInOverSample{ this: CDRInBase =>

  val overCLK = IO(Input(Bool()))
  val sampleRate: Int = 4
  require(sampleRate >= 4)

  val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }

  val flitReg = for( i <- 0 until sampleRate ) yield {
    withClockAndReset(overCLK.asClock, reset.asBool){
      RegNext(
        (sampleReg(i) & sampleReg(i+1)) |
        (sampleReg(i) & sampleReg(i+2)) |
        (sampleReg(i+1) & sampleReg(i+2)), false.B
      )
    }
  }

  val arbCnt  = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
  arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
  val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
  withClockAndReset(overCLK.asClock, reset.asBool){
    when( flitReg(0) ^ flitReg(1) ){
      arbLock := arbCnt
    }


  }

  val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
    Mux1H(
      (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
        //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
      })
    )
  )}


  syncSerDat := ShiftRegister( asyncSerDat, 2 )

}

trait CDRInMultiSample{ this: CDRInBase =>
  val testIO = IO(Output(UInt(3.W)))
  val clkNum: Int = 16


  //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
  val multiCLK = IO(Input(Vec(16, Bool())))


  val sampleReg = Wire(Vec(16, Bool()))
  
  for( i <- 0 until 16 ) {
    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
  }

  val sampleReg_sync = Wire(Vec(23,Bool()))

  for( i <- 0 until 7 ){
    sampleReg_sync(i) := RegNext(sampleReg_sync(i+15))
  }

  for( i <- 7 until 23 ){
    sampleReg_sync(i) := RegNext(sampleReg(i-7))
  }


  val asyncSerDat = PopCount(sampleReg_sync) >= 12.U


    // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U


  syncSerDat := ShiftRegister( asyncSerDat, 2 )


  testIO := Cat( syncSerDat, asyncSerDat, io.serDat )
}



trait CDRInAxis{ this: CDRInBase =>

  def HeaderByte: Int = 4

  val ETH_PRE = "b1100010001".U(10.W)
  val ETH_SFD = "b0110100111".U(10.W)

  val STATE_IDLE = 0.U
  val STATE_HEADER = 1.U
  val STATE_PAYLOAD = 2.U

  val stateNext = Wire(UInt(2.W))
  val stateCurr = RegNext( stateNext, STATE_IDLE )

  val bitCnt = Reg(UInt(4.W))
  val byteCnt = RegInit(0.U((12+1).W))

  val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )

  val shiftData = Dualb4b5Decoder(checkSFD(9,0))

  val payloadLen = RegInit(0.U(12.W))
  when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( shiftData, 0.U(4.W) )
  } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
  }
  
  stateNext := 
    Mux1H(Seq(
      (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
    ))                                                                  //crc





  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
    bitCnt := 0.U
  } .otherwise{
    when( bitCnt === 9.U ){
      bitCnt := 0.U
    } .otherwise{
      bitCnt := bitCnt + 1.U
    }
  }

  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
    byteCnt := 0.U
  } .elsewhen( bitCnt === 9.U ){
    when( stateCurr === STATE_HEADER ){
      byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
      assert( byteCnt <= (HeaderByte-1).U )
    } .elsewhen( stateCurr === STATE_PAYLOAD ){
      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
      assert( byteCnt <= ( payloadLen+ (4-1).U ) )
    }
  }





  val axis_valid = RegInit(false.B)
  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
  val axis_tuser = false.B
  val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )

  io.axis.valid := axis_valid
  io.axis.bits.tdata := axis_tdata
  io.axis.bits.tuser := axis_tuser
  io.axis.bits.tlast := axis_tlast


  when( io.axis.fire ){
    axis_valid := false.B
  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
    axis_valid := true.B
  }

}

class CDRIn extends CDRInBase 
with CDRInAxis
with CDRInOverSample

class MPCDRIn extends CDRInBase 
with CDRInAxis
with CDRInMultiSample