package BACK

import chisel3._
import chisel3.util._



class MasterRegisterBundle extends Bundle{
  val isMstNSlv = Bool()
  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(16.W)

  val isExInfoInit = Bool()
  val isTxReq      = UInt(8.W)
  val txStatus     = UInt(16.W)
  val spiSel       = UInt(2.W)

  val isSoftReset  = Bool()
  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  val intEnable    = UInt(8.W)
  val intMask      = UInt(8.W)
  val intStatus    = UInt(8.W)

  val upRecErrorCnt   = UInt(32.W)
  val downRecErrorCnt = UInt(32.W)

  val upForwardErrorCnt   = UInt(32.W)
  val downForwardErrorCnt = UInt(32.W)

  val qspiErrorCnt   = UInt(32.W)
  val forwardCnt     = UInt(32.W)
  val recByteCnt     = UInt(32.W)
  val forwardByteCnt = UInt(32.W)

  val linkStatus = UInt(8.W)

  val wdtStatus   = UInt(16.W)
  val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val deltaTime = UInt(32.W)
}


class SlaveRegisterBundle extends Bundle{
  val isMstNSlv = Bool()
  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(16.W)

  val RAMSize   = UInt(8.W)
  val MMUNum    = UInt(8.W)

  val nodeSeqAddr = UInt(16.W)
  val nodeSetAddr = UInt(16.W)

  val spiSel       = UInt(2.W)

  val isSoftReset  = Bool()
  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  val ebmmu = Vec(8, new Bundle{
    val logicAddr = UInt(32.W)
    val length = UInt(16.W)
    val phyAddr = UInt(32.W)
    val op = UInt(2.W)
    val enable = Bool()
  })

  val intStatus = UInt(16.W)
  val mb = Vec(8, new Bundle{
    val ctrl = UInt(8.W)
    val status = UInt(8.W)
  })

  val upRecErrorCnt   = UInt(32.W)
  val downRecErrorCnt = UInt(32.W)

  val upForwardErrorCnt   = UInt(32.W)
  val downForwardErrorCnt = UInt(32.W)

  val qspiErrorCnt   = UInt(32.W)
  val forwardCnt     = UInt(32.W)
  val recByteCnt     = UInt(32.W)
  val forwardByteCnt = UInt(32.W)

  val linkStatus = UInt(8.W)

  val wdtStatus   = UInt(16.W)
  val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
  val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
  val mstTimeStamp  = UInt(64.W) //主站时间戳
  val deltaTime = UInt(32.W)

  val dcSyncEnable = Bool()
  val dcSyncWidth  = UInt(16.W)
}

class SPIInterfaceIO extends Bundle{
  val sck  = Input(Bool())
  val csn  = Input(Bool())
  val mosi = Input(Bool())
  val miso = Output(Bool())
}

class InterfaceIO extends Bundle{
  val spi = new SPIInterfaceIO

  val req = Valid(new Bundle{
    val addr = UInt(16.W)
    val dataw = UInt(8.W)
    val isWRn = Bool()
  })

  val resp = Valid(new Bundle{
    datar = UInt(8.W)
  })
}


abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)










  // val softReset = Reg(Bool())
  // val logicAddr = Reg(UInt(30.W))
  // val logicLength = Reg(UInt(16.W))
  // val phyAddr - Reg(UInt(16.W))


}





class Interface extends InterfaceBase{

}