package BACK

import chisel3._
import chisel3.util._





trait LocalRegisters { this: BackBoardSlvBase =>

  val digitalDir = RegInit(0.U(32.W))
  val digitalOut = RegInit(0.U(32.W))
  val digitalIn  = WireDefault(0.U(32.W))

  registersRD := Mux1H(Seq(
    (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn,
  ))

  when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
    when(upStreamReq.io.latDat.bits.register === 0.U){
      digitalDir := upStreamReq.io.latDat.bits.data
    }
    when(upStreamReq.io.latDat.bits.register === 1.U){
      digitalOut := upStreamReq.io.latDat.bits.data
    }
  }


}