.PHONY:com sim clean OUTPUT = shin_test CPU_COUNT := $(shell nproc) SPI_TYPE ?= -spi 0 TRANS_CODE ?= DEVCLK ?= --dev1 0 90 --dev2 0 -88 CDR_TYPE ?= -cdr 0 VCS = vcs -sverilog +v2k -timescale=1ns/1ps \ -full64 \ -o ${OUTPUT} \ -l compile.log \ -debug_access+none \ +define+VCS_COMPILE \ -fastpartcomp=j${CPU_COUNT} \ SIM = ./${OUTPUT} -l run.log testShin_vcs: python3 ./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} mkdir -p generated/log rm -rf generated/log/* @echo "Available CPUs: ${CPU_COUNT}" ${VCS} -f ./shinTest_vcs.f 1>vcs_compile.log 2>&1 ${SIM} python3 ./shinTest/check_testcase.py testShinClk_vcs: python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE} mkdir -p generated/log rm -rf generated/log/* ${VCS} -f ./shinTestClk_vcs.f 1>vcs_compile.log 2>&1 ${SIM} python3 ./shinTest/check_testcase.py testShinMany_vcs: python3 ./shinTest/gen_pkt_many_dev.py mkdir -p generated/log rm -rf generated/log/* @echo "Available CPUs: ${CPU_COUNT}" ${VCS} -f ./shinTest_vcs.f ${SIM} python3 ./shinTest/check_testcase.py sim: ${SIM} testShin: ./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} mkdir -p generated/log rm -rf generated/log/* iverilog -Wall \ -o ./generated/shinTest.iverilog \ -y ./generated/shin \ -I ./generated/shin \ -D RANDOMIZE_REG_INIT \ ./shinTest/ShinTopSpiTb.v vvp -N ./generated/shinTest.iverilog -lxt2 -fst || true ./shinTest/check_testcase.py testShinClk: ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE} mkdir -p generated/log rm -rf generated/log/* iverilog -Wall \ -o ./generated/shinTest_clk.iverilog \ -y ./generated/shin \ -I ./generated/shin \ -D RANDOMIZE_REG_INIT \ ./shinTest/ShinTopSpiTb_clk.v vvp -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true ./shinTest/check_testcase.py fstShin: gtkwave ./generated/wave.fst 1>/dev/null 2>&1 & fstShinClk: gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 & clean: rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*