/*
  Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>

   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at

       http://www.apache.org/licenses/LICENSE-2.0

   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
*/


#include <verilated.h>
#include "VBackBoardSlvTest.h"
#include <memory>
#include <iostream>
#include <getopt.h>

#include <sstream>



#if VM_TRACE
#include "verilated_fst_c.h"
#endif


char* img;
VBackBoardSlvTest *top;
#if VM_TRACE
VerilatedFstC* tfp;
#endif
vluint64_t main_time = 0;

double sc_time_stamp () {
	return main_time;
}



static void sim_exit(){
#if VM_TRACE
	tfp->close();
#endif

	top->final();

	delete top;
}






int main(int argc, char **argv, char **env) {


	top = new VBackBoardSlvTest();

#if VM_TRACE
	tfp = new VerilatedFstC;
    Verilated::traceEverOn(true);
    top->trace(tfp, 99); // Trace 99 levels of hierarchy
    tfp->open("./tb/build/wave.fst");		
#endif




	top->reset   = 1;
	top->clock   = 0;
    top->io_clk4 = 0;
	
	while(!Verilated::gotFinish()) {

		Verilated::timeInc(1);

		if ( main_time != 1000 ){
		} else {
			top->reset = 0;
		}

		if ( main_time % 400 == 100 ) {
			top->clock = 1;
		} else if ( main_time % 400 == 300 ) {
			top->clock = 0;
		} 

		if ( main_time % 100 == 10 ) {
			top->io_clk4 = 1;
		} else if ( main_time % 100 == 60 ) {
			top->io_clk4 = 0;
		}
        

        if( main_time == 50000 ){
            top->io_req_valid = 1;
            top->io_req_bits_address = 0x12;
            top->io_req_bits_register = 0x0;
            top->io_req_bits_data = 0xaa;
        } else if( main_time == 50400 ){
            top->io_req_valid = 0;
        }

        if( main_time == 100000 ){
            top->io_rsp_valid = 1;
            top->io_rsp_bits_address = 0x12;
            top->io_rsp_bits_register = 0x0;
            top->io_rsp_bits_data = 0xaa;
        } else if( main_time == 100400 ){
            top->io_rsp_valid = 0;
        }


		top->eval();
#if VM_TRACE
		tfp->dump(Verilated::time());			

#endif


		main_time ++;

        if( main_time > 200000 ){
            break;
        }
	}
	
	sim_exit();
	return -1;


}