package BACK

import chisel3._
import chisel3.util._


class CDROutBusIO() extends Bundle{
  val pkgDat = Flipped(Decoupled(new CDRData))
  val dat    = Output(Bool())

}

class CDROutBus extends Module{
  val io: CDROutBusIO = IO(new CDROutBusIO)

  val isBusy = RegInit(false.B)
  io.pkgDat.ready := ~isBusy
  
  val address  = Reg(UInt(6.W))
  val register = Reg(UInt(8.W))
  val data     = Reg(UInt(32.W))
  val hash     = Reg(UInt(16.W))

  val cnt = RegInit( 0.U(7.W) )


  when( cnt === (1+6+8+32+16).U ){
    isBusy := false.B
  } .elsewhen( io.pkgDat.fire ){
    isBusy := true.B

    address  := io.pkgDat.bits.address
    register := io.pkgDat.bits.register
    data     := io.pkgDat.bits.data

  }

  when(io.pkgDat.fire){
    cnt := 0.U
  } .elsewhen( isBusy ){
    cnt := cnt + 1.U
  }



  when( cnt === 0.U ){
    io.dat := true.B
  } .elsewhen( cnt >= (0 + 1).U && cnt < (6 + 1).U ){
    io.dat := address(5)
    address := address << 1
  } .elsewhen( cnt >= (0 + 1 + 6).U && cnt < (8 + 1 + 6).U ){
    io.dat := register(7)
    register := register << 1
  } .elsewhen( cnt >= (0 + 1 + 6 + 8).U && cnt < (32 + 1 + 6 + 8).U ){
    io.dat := data(31)
    data := data << 1
  } .elsewhen( cnt >= (0 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 6 + 8 + 32).U ){
    io.dat := hash(15)
    hash := hash << 1
  } .otherwise{
    io.dat := false.B
  }

}