TARGET=riscv64-unknown-elf
RVCC=$(TARGET)-gcc
RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
MARCH=-march=rv32i -mabi=ilp32
CFLAGS=-O2
ifeq "$(RVCCVERSION)" "12.2.0"
   	MARCH=-march=rv32izicsr -mabi=ilp32
endif

.PHONY: compile tb wave

compile:
	rm -rf ./generated/Rtpp
	rm -rf ./rocket-chip/vsim/generated-src/
	mkdir -p ./generated/Rtpp
	cd ./rocket-chip/ && rm -f rocketchip.jar
	cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig
	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
# 	sbt "test:runMain test.testModule"

back:
	rm -f ./generated/back/*
	rm -f ./generated/cdr/*
	sbt "test:runMain test.testModule"
	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
	cp ./src/main/verilog/oser_rst.v ./generated/back/
	cp ./src/main/verilog/di16_top.v ./generated/back/
	cp ./src/main/verilog/do16_top.v ./generated/back/
	cp ./src/main/verilog/do16inv_top.v ./generated/back/
	cp ./src/main/verilog/qei_top.v ./generated/back/
	cp ./src/main/verilog/spi_top.v ./generated/back/
	cp ./src/main/verilog/defineParam.v ./generated/back/


ef: 
	sbt "test:runMain test.testModule"

VSimTop: 
	rm -rf ./tb/build/
	mkdir -p ./tb/build/
	verilator -Wno-fatal  \
	-y ${PWD}/generated/Rtpp/ \
	-y ${PWD}/tb/verilator/ \
	--top-module SimTop \
	--trace-fst \
	--cc ./tb/verilator/SimTop.v  \
	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_DELAY=0 \
	--exe --build \
	${PWD}/tb/verilator/sim_main.cpp \
	-Mdir ./tb/build/ \
	-j 30

	# +define+RANDOMIZE_MEM_INIT

test:
	./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest




sw:
	rm ./tb/sw/build/* -f
	mkdir -p ./tb/sw/build/

	$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-I ./tb/sw/tl2cdr \
	-c ./tb/sw/src/mstStartup.S \
	-o ./tb/sw/build/mstStartup.o

	$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-I ./tb/sw/tl2cdr \
	-c ./tb/sw/src/MstMain.c \
	-o ./tb/sw/build/mstMain.o

	# $(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	# -I ./tb/sw/ -I ./tb/sw/src \
	# -c ./tb/sw/src/mstMain.S \
	# -o ./tb/sw/build/mstMain.o

	$(RVCC) -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
	-T ./tb/sw/linker.lds \
	./tb/sw/build/mstStartup.o \
	./tb/sw/build/mstMain.o \
	-o ./tb/sw/build/mstTest.elf

	$(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.bin
	
	$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump

	$(TARGET)-objcopy -O verilog  ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.verilog
	sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog



	$(RVCC) -O3 -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-I ./tb/sw/tl2cdr \
	-c ./tb/sw/src/SlvMain.c \
	-o ./tb/sw/build/slvMain.o

	$(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-c ./tb/sw/src/slvStartup.S \
	-o ./tb/sw/build/slvStartup.o

	# $(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	# -I ./tb/sw/ -I ./tb/sw/src \
	# -c ./tb/sw/src/slvMain.S \
	# -o ./tb/sw/build/slvMain.o

	$(RVCC) -Os -ggdb $(MARCH) $(CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
	-T ./tb/sw/linker.lds \
	./tb/sw/build/slvStartup.o \
	./tb/sw/build/slvMain.o \
	-o ./tb/sw/build/slvTest.elf

	$(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.bin

	$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump

	$(TARGET)-objcopy -O verilog  ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.verilog
	sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog

	python3 ./tb/sw/bin_to_hex.py
	python3 ./tb/sw/bin_to_coe.py


fst:
	gtkwave ./tb/build/wave.fst &



VSimBack: 
	rm -rf ./tb/build/
	mkdir -p ./tb/build/
	verilator -Wno-fatal  \
	--timescale "1 ns / 1 ps" \
	-y ${PWD}/tb/ \
	-y ${PWD}/generated/ \
	--top-module BackPlaneChainTest \
	--trace-fst \
	--cc ./generated/BackPlaneChainTest.v  \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_MEM_INIT \
	+define+RANDOMIZE_DELAY=0 \
	--exe --build \
	${PWD}/tb/sim_backChain.cpp \
	-Mdir ./tb/build/ \
	-j 30



tb:
	iverilog -Wall \
	-o ./build/wave.iverilog  \
	-y ./tb  \
	-y ./generated/cdr/  \
	-I ./tb  \
	-I ./generated/cdr/  \
	-D RANDOMIZE_REG_INIT \
	./tb/backSys_tb.v 
	vvp  -N ./build/wave.iverilog -lxt2

vcd:
	gtkwave ./build/wave.vcd &