package BACK

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._


class SimpleGpio()(implicit p: Parameters) extends BackModule{
  class SimpleGpioIO extends Bundle{
    val mem = Flipped(new Mem_Port_Bundle)

    val out = Output(UInt(32.W))
    val in  = Input(UInt(32.W))


    val isOnline = Output(Bool())
    val isLast   = Input(Bool())

  }

  val io: SimpleGpioIO = IO(new SimpleGpioIO)

  val isWriteGpio  = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb =/= 0.U
  val isReadGpio   = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb === 0.U
  // val isWriteDir   = io.mem.fire & io.mem.addr(3,0) === "h4".U & io.mem.wstrb =/= 0.U
  val isReadIsLast = io.mem.fire & io.mem.addr(3,0) === "h8".U & io.mem.wstrb === 0.U


  io.isOnline := false.B

  io.out := RegEnable( io.mem.wdata, 0.U(32.W), isWriteGpio )

  io.mem.ready := true.B
  io.mem.rdata :=
    Mux( io.mem.addr(3,0) === "h0".U, io.in, 
      Mux( io.mem.addr(3,0) === "h8".U, io.isLast, 0.U ) )

}