`timescale 1 ns / 1 ps `define ENABLE_REG_RW_TEST `define ENABLE_DET_TEST `define ENABLE_SET_ADDR_TEST `define ENABLE_INT_INIT_TEST //`define ENABLE_SM1_SEND_TEST //`define ENABLE_SMx_SEND_TEST //`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST `define ENABLE_EXCHG_DATA_SEQ2_TEST //`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST //`define ENABLE_BC_W_TEST //`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST //`define ENABLE_SYNC_SIG0_TEST //`define ENABLE_SYNC_SIG1_TEST //`define ENABLE_RESET_TEST //`define ENABLE_EBMMU_TC1_TEST //`define ENABLE_EBMMU_TC2_TEST //`define ENABLE_EBMMU_TC3_TEST //`define ENABLE_EBMMU_TC4_TEST module ShinTopSpiTb( ); reg clock; reg reset; reg clk8x; wire [3:0] dDat_w; wire [3:0] uDat_w; wire spi_sck; wire spi_mosi; wire [4:0] spi_miso; reg [14:0] spi_csn; wire qspi_sck; wire [3:0] qspi_mosi; wire [40-1:0] qspi_miso; wire isResp; integer spidata_file; integer c_line; integer _pos; integer _len; integer _t_start; integer _t_end; reg [63:0] _temp_time; reg _reset_deactive; wire [4:0] isSoftReset; wire [4:0] io_int_sig; ShinTop s_ShinTop_Mst( .clock(clock), .reset(reset | isSoftReset[0]), .io_clk8x(clk8x), .io_dDatIn(1'b0), .io_dDatOut(dDat_w[0]), .io_uDatIn(uDat_w[0]), .io_uDatOut(), .io_iqspi_sck(qspi_sck), .io_iqspi_mosi(qspi_mosi), .io_iqspi_miso(qspi_miso[3:0]), .io_iqspi_isDirIn(), .io_iqspi_csn(spi_csn[0]), .io_ospi_sck (spi_sck), .io_ospi_mosi(spi_mosi), .io_ospi_miso(spi_miso[0]), .io_ospi_csn (spi_csn[5]), .io_oqspi_sck(qspi_sck), .io_oqspi_mosi(qspi_mosi), .io_oqspi_miso(qspi_miso[4*5+3:4*5]), .io_oqspi_isDirIn(), .io_oqspi_csn(spi_csn[10]), .io_rsp_valid(isResp), .io_rsp_bits_isError(), .io_isSoftReset(isSoftReset[0]), .io_interrupt(io_int_sig[0]) ); ShinTop s_ShinTop_slv0( .clock(clock), .reset(reset | isSoftReset[1]), .io_clk8x(clk8x), .io_dDatIn(dDat_w[0]), .io_dDatOut(dDat_w[1]), .io_uDatIn(uDat_w[1]), .io_uDatOut(uDat_w[0]), .io_iqspi_sck(qspi_sck), .io_iqspi_mosi(qspi_mosi), .io_iqspi_miso(qspi_miso[4*1+3:4*1]), .io_iqspi_isDirIn(), .io_iqspi_csn(spi_csn[1]), .io_ospi_sck (spi_sck), .io_ospi_mosi(spi_mosi), .io_ospi_miso(spi_miso[1]), .io_ospi_csn (spi_csn[6]), .io_oqspi_sck(qspi_sck), .io_oqspi_mosi(qspi_mosi), .io_oqspi_miso(qspi_miso[4*6+3:4*6]), .io_oqspi_isDirIn(), .io_oqspi_csn(spi_csn[11]), .io_rsp_valid(), .io_rsp_bits_isError(), .io_isSoftReset(isSoftReset[1]), .io_interrupt(io_int_sig[1]) ); ShinTop s_ShinTop_slv1( .clock(clock), .reset(reset | isSoftReset[2]), .io_clk8x(clk8x), .io_dDatIn(dDat_w[1]), .io_dDatOut(dDat_w[2]), .io_uDatIn(uDat_w[2]), .io_uDatOut(uDat_w[1]), .io_iqspi_sck(qspi_sck), .io_iqspi_mosi(qspi_mosi), .io_iqspi_miso(qspi_miso[4*2+3:4*2]), .io_iqspi_isDirIn(), .io_iqspi_csn(spi_csn[2]), .io_ospi_sck (spi_sck), .io_ospi_mosi(spi_mosi), .io_ospi_miso(spi_miso[2]), .io_ospi_csn (spi_csn[7]), .io_oqspi_sck(qspi_sck), .io_oqspi_mosi(qspi_mosi), .io_oqspi_miso(qspi_miso[4*7+3:4*7]), .io_oqspi_isDirIn(), .io_oqspi_csn(spi_csn[12]), .io_rsp_valid(), .io_rsp_bits_isError(), .io_isSoftReset(isSoftReset[2]), .io_interrupt(io_int_sig[2]) ); ShinTop s_ShinTop_slv2( .clock(clock), .reset(reset | isSoftReset[3]), .io_clk8x(clk8x), .io_dDatIn(dDat_w[2]), .io_dDatOut(dDat_w[3]), .io_uDatIn(uDat_w[3]), .io_uDatOut(uDat_w[2]), .io_iqspi_sck(qspi_sck), .io_iqspi_mosi(qspi_mosi), .io_iqspi_miso(qspi_miso[4*3+3:4*3]), .io_iqspi_isDirIn(), .io_iqspi_csn(spi_csn[3]), .io_ospi_sck (spi_sck), .io_ospi_mosi(spi_mosi), .io_ospi_miso(spi_miso[3]), .io_ospi_csn (spi_csn[8]), .io_oqspi_sck(qspi_sck), .io_oqspi_mosi(qspi_mosi), .io_oqspi_miso(qspi_miso[4*8+3:4*8]), .io_oqspi_isDirIn(), .io_oqspi_csn(spi_csn[13]), .io_rsp_valid(), .io_rsp_bits_isError(), .io_isSoftReset(isSoftReset[3]), .io_interrupt(io_int_sig[3]) ); ShinTop s_ShinTop_slv3( .clock(clock), .reset(reset | isSoftReset[4]), .io_clk8x(clk8x), .io_dDatIn(dDat_w[3]), .io_dDatOut(), .io_uDatIn(1'b0), .io_uDatOut(uDat_w[3]), .io_iqspi_sck(qspi_sck), .io_iqspi_mosi(qspi_mosi), .io_iqspi_miso(qspi_miso[4*4+3:4*4]), .io_iqspi_isDirIn(), .io_iqspi_csn(spi_csn[4]), .io_ospi_sck (spi_sck), .io_ospi_mosi(spi_mosi), .io_ospi_miso(spi_miso[4]), .io_ospi_csn (spi_csn[9]), .io_oqspi_sck(qspi_sck), .io_oqspi_mosi(qspi_mosi), .io_oqspi_miso(qspi_miso[4*9+3:4*9]), .io_oqspi_isDirIn(), .io_oqspi_csn(spi_csn[14]), .io_rsp_valid(), .io_rsp_bits_isError(), .io_isSoftReset(isSoftReset[4]), .io_interrupt(io_int_sig[4]) ); initial begin clock = 0; clk8x = 0; reset = 1; _reset_deactive = 1'b0; $timeformat(-9, 2, " ns", 8); spi_csn = ~15'b0; #100 reset <= 1; #240 reset <= 0; //#20000000 #1000000000 //#5000000 $display("Time Out !!!"); $fclose(spidata_file); $stop; end initial begin forever begin #20 clk8x <= ~clk8x; end end initial begin forever begin #80 clock <= ~clock; end end initial begin spidata_file = $fopen("spi_trans_data.txt", "w"); if (!spidata_file) $display("文件打开失败"); $dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称 $dumpvars(0, ShinTopSpiTb);//tb模块名称 end always @(posedge reset) begin _reset_deactive <= 1'b0; end always @(negedge reset) begin _reset_deactive <= 1'b1; end `define SCKFRE #640 reg sck = 0; initial begin forever begin `SCKFRE sck <= ~sck; end end assign spi_sck = sck; assign qspi_sck = sck; reg [7:0] txBuf[0:2047]; reg [7:0] rxBuf[0:2047]; reg [7:0] exChangeRego; reg [7:0] exChangeRegi; assign spi_mosi = exChangeRego[7]; assign qspi_mosi = exChangeRego[7:4]; wire [3:0] qspi_mux_miso = ( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) | ( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) | ( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) | ( qspi_miso[4*3+3:4*3] & ~{4{spi_csn[ 3]}}) | ( qspi_miso[4*4+3:4*4] & ~{4{spi_csn[ 4]}}) | ( qspi_miso[4*5+3:4*5] & ~{4{spi_csn[10]}}) | ( qspi_miso[4*6+3:4*6] & ~{4{spi_csn[11]}}) | ( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) | ( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) | ( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}}); wire spi_mux_miso = ( spi_miso[0] & ~spi_csn[5] ) | ( spi_miso[1] & ~spi_csn[6] ) | ( spi_miso[2] & ~spi_csn[7] ) | ( spi_miso[3] & ~spi_csn[8] ) | ( spi_miso[4] & ~spi_csn[9] ); reg isReq = 0; reg isBusy = 0; reg [11:0] length; reg [7:0] idx; reg [11:0] transCnt; reg [11:0] byteCnt; reg [2:0] bitCnt; always @(posedge clock) begin if( isReq & sck == 0 ) begin isBusy <= #5 1'b1; transCnt <= #5 0; byteCnt <= #5 ~12'b0; bitCnt <= #5 ~3'b0; spi_csn[idx] <= #5 1'b0; exChangeRego <= txBuf[0]; end end wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10; wire [11:0] nextByteCnt = byteCnt + 1; //输出 always @(negedge sck) begin if( isBusy ) begin if( &bitCnt ) begin exChangeRego <= txBuf[nextByteCnt]; end else begin exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1; end end end //输入 always @(posedge sck) begin if( isBusy ) begin if( transCnt <= length ) begin if( isQspi ) begin bitCnt <= ~bitCnt; end else begin bitCnt <= bitCnt + 1; end if( &bitCnt ) begin byteCnt <= byteCnt +1; transCnt <= transCnt + 1; if( txBuf[2] === 1 & nextByteCnt >= 4) begin rxBuf[byteCnt] <= exChangeRegi; //$display("spi read out %x", exChangeRegi); end if( txBuf[2] === 1 & nextByteCnt >= 3) begin exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; end else begin exChangeRegi <= 0; end end else begin exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; end end else begin isBusy <= #5 1'b0; spi_csn[idx] <= #5 1'b1; end end end //mst slv0~slv3的 内部qspi调用即设置 //sidx为0~4;外部spi为5~9,外部qspi为10~15 task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx ); begin txBuf[0] <= saddress[15:8]; txBuf[1] <= saddress[7:0]; txBuf[2] <= scmd; length <= slength + 3; idx <= sidx; #5 @(negedge sck) isReq <= 1; @(posedge sck) #5 isReq <= 0; @( negedge isBusy) #1000 begin //$fwrite(spidata_file, "------------%5t------------\n", $realtime); $fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n", $realtime, ((sidx >= 5)? ((sidx >= 10)? (sidx - 10):(sidx - 5)):sidx), txBuf[0], txBuf[1], ((txBuf[2] == 0)? "Write":" Read"), slength); if ( ((saddress == 16'h0800) || (saddress == 16'h1000) || (saddress == 16'h1800) || (saddress == 16'h2000) || (saddress == 16'h2800) || (saddress == 16'h3000) || (saddress == 16'h3800) || (saddress == 16'h4000)) && ((sidx == 0) || (sidx == 5) || (sidx == 10))) begin _pos = 3; for (integer _k = 0; _k < 4; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); end else begin $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); end end $fwrite(spidata_file, "\n"); _pos = 4 + _pos; for (; _pos < slength; ) begin for (integer _k = 0; _k < 6; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); _len = txBuf[_pos + 5] + (txBuf[_pos + 4] & 8'h0f) * 256; end else begin $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); _len = rxBuf[_pos + 5] + (rxBuf[_pos + 4] & 8'h0f) * 256; end end $fwrite(spidata_file, "\n{{ "); _pos = _pos + 6; for (integer _k = 0; _k < _len; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); end else begin $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); end c_line = 0; if ((_k + 2)%16 == 0) begin $fwrite(spidata_file, "\n"); c_line = 1; end end $fwrite(spidata_file, "}}\n"); _pos = _pos + _len; for (integer _k = 0; _k < 2; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); end else begin $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); end end _pos = _pos + 2; $fwrite(spidata_file, "\n"); end end else begin for (integer i=0; i