|
|
fd1f0d1536
|
增加新的测试用例，调整内部的延时。±176ppm测试通过，184ppm测试未通过，但差得字节数并不多，最终偏差大概在180ppm上下
|
2025-09-02 00:31:40 +08:00 |
|
|
|
43a0df6da7
|
增加200ppm的测试代码,200ppm测试没有通过,但160ppm/120ppm测试通过
|
2025-09-01 19:50:35 +08:00 |
|
|
|
cce1cf4179
|
增加测试用例,将频率差改到120ppm,测试未通过
|
2025-09-01 17:00:19 +08:00 |
|
|
|
0c9c52a57a
|
修复主分支下的multiclk产生的错误
|
2025-09-01 16:31:27 +08:00 |
|
|
|
08f602ab1b
|
合并通讯线路的交叉功能,为环网做准备
|
2025-09-01 16:18:25 +08:00 |
|
|
|
b8da95422e
|
修改测试用例, 80ppm通过
|
2025-09-01 16:12:37 +08:00 |
|
|
|
a5919e29c0
|
增加测试用例29
|
2025-08-30 14:55:25 +08:00 |
|
|
|
0bb9f89969
|
修正测试用例
|
2025-08-30 14:54:10 +08:00 |
|
|
|
25577a4d50
|
增加测试代码
|
2025-08-30 14:32:05 +08:00 |
|
|
|
0bcb947a2d
|
增加线路交叉的测试用例
|
2025-08-30 13:04:17 +08:00 |
|
|
|
17a6f5a3f8
|
增加测试用例
|
2025-08-29 17:20:40 +08:00 |
|
|
|
e9d412561e
|
增加频率差160ppm的测试代码
|
2025-08-29 16:45:11 +08:00 |
|
Ruige Lee
|
60eec33b2d
|
上下行交换特性
|
2025-08-29 15:37:29 +08:00 |
|
Ruige Lee
|
51d29f1dd7
|
Merge branch 'mp_eb_dev' into feature/dwupEx
|
2025-08-29 11:12:53 +08:00 |
|
Ruige Lee
|
1a01fa9d72
|
CDR仿真文件
|
2025-08-28 20:06:14 +08:00 |
|
Ruige Lee
|
08f74c6986
|
Merge branch 'feature/cdrSim' into mp_eb_dev
|
2025-08-28 20:04:30 +08:00 |
|
Ruige Lee
|
bbfc0322e9
|
增加CDR仿真例程
|
2025-08-28 20:03:42 +08:00 |
|
Ruige Lee
|
955fda6d05
|
spi优化
|
2025-08-28 18:00:20 +08:00 |
|
Ruige Lee
|
55ea876488
|
同上
|
2025-08-28 16:10:57 +08:00 |
|
Ruige Lee
|
659ab14fab
|
修改同步点调整逻辑
|
2025-08-28 15:53:17 +08:00 |
|
Ruige Lee
|
4b88e4937d
|
改时序
|
2025-08-28 15:51:17 +08:00 |
|
Ruige Lee
|
9bb59c350a
|
Revert "Revert "改命令""
This reverts commit a0320e1993.
|
2025-08-28 13:08:50 +08:00 |
|
Ruige Lee
|
a0320e1993
|
Revert "改命令"
This reverts commit ea7ef3c9f9.
|
2025-08-28 13:05:37 +08:00 |
|
Ruige Lee
|
ea7ef3c9f9
|
改命令
|
2025-08-28 13:05:17 +08:00 |
|
Ruige Lee
|
d4c793bf0b
|
修正同步宽度不能spi修改的问题
|
2025-08-28 11:07:57 +08:00 |
|
Ruige Lee
|
985407a8a4
|
新spi设计
|
2025-08-28 11:03:33 +08:00 |
|
|
|
6d6e07346b
|
增加主站的同步输出
|
2025-08-28 10:49:58 +08:00 |
|
Ruige Lee
|
f5336f1dc5
|
硬件错误中断捕捉边缘
|
2025-08-28 10:28:59 +08:00 |
|
|
|
4979a10a72
|
配置测试环境
|
2025-08-28 10:16:55 +08:00 |
|
|
|
39a3f01936
|
增加测试用例
|
2025-08-28 09:59:15 +08:00 |
|
Ruige Lee
|
706b9f17e5
|
FPGA测试通过
|
2025-08-27 17:06:31 +08:00 |
|
Ruige Lee
|
e44373ab83
|
校准时间
|
2025-08-27 16:31:17 +08:00 |
|
Ruige Lee
|
58ad17ce79
|
修复
|
2025-08-27 16:27:00 +08:00 |
|
Ruige Lee
|
a09ccef57f
|
缩短主从同步时间差
|
2025-08-27 16:05:20 +08:00 |
|
Ruige Lee
|
9773752cc8
|
上下行交换特性
|
2025-08-27 15:55:09 +08:00 |
|
Ruige Lee
|
fa3ba57f32
|
spi写pll寄存器信号拉到顶层
|
2025-08-27 15:20:43 +08:00 |
|
Ruige Lee
|
bdabf08108
|
Merge branch 'mp_eb_dev' into feature/clk3_shift_allow
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
|
2025-08-27 14:59:39 +08:00 |
|
Ruige Lee
|
dd71c557b7
|
Merge branch 'feature/liftCdr' into mp_eb_dev
|
2025-08-27 14:45:29 +08:00 |
|
Ruige Lee
|
4e2e3f6ca4
|
修复sync的64位加法器输入位宽转换问题
|
2025-08-27 09:42:01 +08:00 |
|
|
|
c69acb4bf0
|
sync不能工作,已确认,需要检查代码
|
2025-08-26 20:35:21 +08:00 |
|
Ruige Lee
|
4b90a2c9bd
|
CDR拉到顶层
|
2025-08-26 17:52:23 +08:00 |
|
|
|
1fe1959f8c
|
增加新的测试用例,测试sync寄存器组的时间读取,以免发生进位错误
|
2025-08-26 17:35:46 +08:00 |
|
|
|
f8065c79c9
|
修正基础库里生成代码的方式，删除不必要的废代码
|
2025-08-26 17:35:46 +08:00 |
|
Ruige Lee
|
c6bd7902e7
|
Merge branch 'mp_eb_dev' into feature/liftCdr
|
2025-08-26 17:07:58 +08:00 |
|
Ruige Lee
|
b821571218
|
同步逻辑扩展delta位宽，使用分时共享64位加法器
|
2025-08-26 17:02:57 +08:00 |
|
Ruige Lee
|
ae99f5801d
|
spi读锁定0x118
|
2025-08-26 15:17:37 +08:00 |
|
Ruige Lee
|
6b118fa498
|
spi读0x100将会暂存后续寄存器防止进位
|
2025-08-26 11:35:47 +08:00 |
|
Ruige Lee
|
72fe230200
|
尝试把CDR提到顶层
|
2025-08-26 10:30:12 +08:00 |
|
Ruige Lee
|
249a94a64b
|
Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
|
2025-08-25 19:17:08 +08:00 |
|
Ruige Lee
|
6f1101f6dc
|
改异步复位，增加flush接口，删除其他工程代码以编译通过
|
2025-08-25 19:16:27 +08:00 |
|
