RuigeLee
|
5f61a4265e
|
产生初始化完成，传输完成，错误中断信号，宽度一个周期(10MHZ)
|
2024-03-20 10:26:31 +08:00 |
|
RuigeLee
|
8d97fff560
|
修复访问FSMC寄存器空间时 锁错data的问题，跟cpu adv宽度有关
|
2024-03-19 19:39:32 +08:00 |
|
RuigeLee
|
0ae44e5c68
|
FSMC写优化后通过
|
2024-03-18 20:01:43 +08:00 |
|
RuigeLee
|
a29c01c812
|
改变读写操作方式，从单次跳变变为持续操作
增加4号测试寄存器，实际地址为4<<1
|
2024-03-16 20:46:35 +08:00 |
|
RuigeLee
|
2b18de45e6
|
没有片选时，AD必须为高阻态
|
2024-03-16 20:45:12 +08:00 |
|
RuigeLee
|
ca60205abc
|
反转FSMC信号电平，尝试测试
|
2024-03-06 17:41:28 +08:00 |
|
RuigeLee
|
ea226e913a
|
输出IO扩展为16个
|
2024-03-06 17:10:51 +08:00 |
|
RuigeLee
|
dba35faa6e
|
主机模拟FSMC模式不能背靠背传送，否则会出CRC以及CDR
|
2024-02-22 16:34:01 +08:00 |
|
RuigeLee
|
411ad21db6
|
新lvds代码仿真目前不影响原功能
|
2024-01-26 17:34:22 +08:00 |
|
RuigeLee
|
d729dfbe7e
|
FSMC跑测试
|
2024-01-09 17:48:23 +08:00 |
|
RuigeLee
|
d74a4754a7
|
FSMC重构，使用100MHZ过采样
|
2024-01-08 18:01:29 +08:00 |
|
Ruige
|
b15cb7117c
|
主从通信正常，注意逻辑分析仪时序影响用户逻辑时序，注意resetn应手动挂1，注意输出io被选为全0
|
2024-01-05 11:24:54 +08:00 |
|
RuigeLee
|
2f09a7245f
|
Revert "stage"
This reverts commit 98b13e6b94.
|
2023-12-27 17:44:50 +08:00 |
|
RuigeLee
|
98b13e6b94
|
stage
|
2023-12-27 17:44:42 +08:00 |
|
RuigeLee
|
afd21f6913
|
临时调试修改，需要revert
|
2023-12-26 14:40:59 +08:00 |
|
RuigeLee
|
1f898a7173
|
提供编译接口
|
2023-12-07 11:10:05 +08:00 |
|
RuigeLee
|
31213302aa
|
尝试流片顶层
|
2023-11-14 17:03:19 +08:00 |
|
RuigeLee
|
b6767e5187
|
dma通路完成，可以承载背靠背负载
|
2023-11-10 15:47:43 +08:00 |
|
RuigeLee
|
a3cc3d1d3d
|
尝试DMA通路，接收好
|
2023-11-09 17:29:33 +08:00 |
|
RuigeLee
|
4285882a7a
|
广播路径很好
|
2023-11-08 16:06:26 +08:00 |
|
RuigeLee
|
c31479f898
|
定向数据流已清
|
2023-11-08 15:41:21 +08:00 |
|
RuigeLee
|
99d3490173
|
编译通过
|
2023-11-07 15:45:31 +08:00 |
|
RuigeLee
|
7d8a4851f9
|
拆分寄存器域，编译有问题
|
2023-11-06 18:56:02 +08:00 |
|
RuigeLee
|
3774d56391
|
remove error
|
2023-11-02 15:25:26 +08:00 |
|
RuigeLee
|
9d08c298de
|
using pingpong buffer
|
2023-11-02 15:16:22 +08:00 |
|
RuigeLee
|
d2e0f567e0
|
调整缓冲区策略，适应高强度调度
|
2023-11-01 16:22:46 +08:00 |
|
RuigeLee
|
5e50dc3148
|
mac dma 抽象成node
|
2023-11-01 14:48:03 +08:00 |
|
RuigeLee
|
7c78948415
|
归一化mac的发送接收buf
|
2023-10-31 17:32:16 +08:00 |
|
RuigeLee
|
eb8420e7f9
|
tx/rx buff接口归一化
|
2023-10-30 17:32:55 +08:00 |
|
RuigeLee
|
beedc98977
|
解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac
|
2023-10-27 18:27:58 +08:00 |
|
RuigeLee
|
ada2f25ff3
|
bug清理完成
|
2023-10-26 15:46:21 +08:00 |
|
RuigeLee
|
530e6d9792
|
编译完成，bug:1 tx 最后一个字节读取了两次，2 先tx无法rx
|
2023-10-26 14:59:31 +08:00 |
|
RuigeLee
|
694d3890b0
|
crc cleanup
|
2023-10-26 11:41:29 +08:00 |
|
RuigeLee
|
b1629ad0a9
|
remvoe pad and minFL
|
2023-10-26 11:32:44 +08:00 |
|
RuigeLee
|
a59a0d9687
|
clean maxFL
|
2023-10-25 18:01:04 +08:00 |
|
RuigeLee
|
09ea816005
|
maccontrol remove
|
2023-10-25 17:53:18 +08:00 |
|
RuigeLee
|
7f8536ec82
|
maccontrol remove
|
2023-10-25 17:52:43 +08:00 |
|
RuigeLee
|
1e6f2df9ae
|
clean up
|
2023-10-25 16:04:53 +08:00 |
|
RuigeLee
|
6e25f934b2
|
remove tx toobig
|
2023-10-25 15:34:43 +08:00 |
|
RuigeLee
|
811c540b6b
|
remove tx retry
|
2023-10-25 15:21:43 +08:00 |
|
RuigeLee
|
8fad6fc9cb
|
remove rxabort again
|
2023-10-25 14:33:48 +08:00 |
|
RuigeLee
|
3e4964852e
|
人机交互界面完成
|
2023-10-24 17:42:25 +08:00 |
|
RuigeLee
|
e99ff4789f
|
tx 首尾修正
|
2023-10-24 16:27:30 +08:00 |
|
RuigeLee
|
701ba16491
|
cleanup
|
2023-10-24 15:34:30 +08:00 |
|
RuigeLee
|
86fb086bd2
|
tx 32转8 基本测试通过
|
2023-10-24 14:00:51 +08:00 |
|
RuigeLee
|
54991d8cb5
|
Tx尝试统一接口，失败
|
2023-10-23 23:36:01 +08:00 |
|
RuigeLee
|
faa46be8ef
|
Rx的req resp跨时钟架构
|
2023-10-23 22:58:36 +08:00 |
|
RuigeLee
|
bf66bae475
|
rx 通道基本完成32转8，存在跨时钟域风险
|
2023-10-21 21:08:40 +08:00 |
|
RuigeLee
|
69ccc32603
|
在32数据通道下传输正确
|
2023-10-20 20:56:44 +08:00 |
|
RuigeLee
|
f17d405369
|
Rx DMA 传输正确
|
2023-10-20 15:49:24 +08:00 |
|