RuigeLee
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411ad21db6
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新lvds代码仿真目前不影响原功能
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2024-01-26 17:34:22 +08:00 |
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RuigeLee
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d729dfbe7e
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FSMC跑测试
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2024-01-09 17:48:23 +08:00 |
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RuigeLee
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d74a4754a7
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FSMC重构，使用100MHZ过采样
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2024-01-08 18:01:29 +08:00 |
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Ruige
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b15cb7117c
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主从通信正常，注意逻辑分析仪时序影响用户逻辑时序，注意resetn应手动挂1，注意输出io被选为全0
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2024-01-05 11:24:54 +08:00 |
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RuigeLee
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2f09a7245f
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Revert "stage"
This reverts commit 98b13e6b94.
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2023-12-27 17:44:50 +08:00 |
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RuigeLee
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98b13e6b94
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stage
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2023-12-27 17:44:42 +08:00 |
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RuigeLee
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afd21f6913
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临时调试修改，需要revert
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2023-12-26 14:40:59 +08:00 |
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RuigeLee
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1f898a7173
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提供编译接口
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2023-12-07 11:10:05 +08:00 |
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RuigeLee
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31213302aa
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尝试流片顶层
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2023-11-14 17:03:19 +08:00 |
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RuigeLee
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b6767e5187
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dma通路完成，可以承载背靠背负载
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2023-11-10 15:47:43 +08:00 |
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RuigeLee
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a3cc3d1d3d
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尝试DMA通路，接收好
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2023-11-09 17:29:33 +08:00 |
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RuigeLee
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4285882a7a
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广播路径很好
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2023-11-08 16:06:26 +08:00 |
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RuigeLee
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c31479f898
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定向数据流已清
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2023-11-08 15:41:21 +08:00 |
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RuigeLee
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99d3490173
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编译通过
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2023-11-07 15:45:31 +08:00 |
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RuigeLee
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7d8a4851f9
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拆分寄存器域，编译有问题
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2023-11-06 18:56:02 +08:00 |
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RuigeLee
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3774d56391
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remove error
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2023-11-02 15:25:26 +08:00 |
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RuigeLee
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9d08c298de
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using pingpong buffer
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2023-11-02 15:16:22 +08:00 |
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RuigeLee
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d2e0f567e0
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调整缓冲区策略，适应高强度调度
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2023-11-01 16:22:46 +08:00 |
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RuigeLee
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5e50dc3148
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mac dma 抽象成node
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2023-11-01 14:48:03 +08:00 |
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RuigeLee
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7c78948415
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归一化mac的发送接收buf
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2023-10-31 17:32:16 +08:00 |
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RuigeLee
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eb8420e7f9
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tx/rx buff接口归一化
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2023-10-30 17:32:55 +08:00 |
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RuigeLee
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beedc98977
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解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac
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2023-10-27 18:27:58 +08:00 |
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RuigeLee
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ada2f25ff3
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bug清理完成
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2023-10-26 15:46:21 +08:00 |
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RuigeLee
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530e6d9792
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编译完成，bug:1 tx 最后一个字节读取了两次，2 先tx无法rx
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2023-10-26 14:59:31 +08:00 |
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RuigeLee
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694d3890b0
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crc cleanup
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2023-10-26 11:41:29 +08:00 |
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RuigeLee
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b1629ad0a9
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remvoe pad and minFL
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2023-10-26 11:32:44 +08:00 |
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RuigeLee
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a59a0d9687
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clean maxFL
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2023-10-25 18:01:04 +08:00 |
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RuigeLee
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09ea816005
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maccontrol remove
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2023-10-25 17:53:18 +08:00 |
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RuigeLee
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7f8536ec82
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maccontrol remove
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2023-10-25 17:52:43 +08:00 |
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RuigeLee
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1e6f2df9ae
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clean up
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2023-10-25 16:04:53 +08:00 |
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RuigeLee
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6e25f934b2
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remove tx toobig
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2023-10-25 15:34:43 +08:00 |
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RuigeLee
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811c540b6b
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remove tx retry
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2023-10-25 15:21:43 +08:00 |
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RuigeLee
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8fad6fc9cb
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remove rxabort again
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2023-10-25 14:33:48 +08:00 |
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RuigeLee
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3e4964852e
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人机交互界面完成
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2023-10-24 17:42:25 +08:00 |
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RuigeLee
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e99ff4789f
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tx 首尾修正
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2023-10-24 16:27:30 +08:00 |
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RuigeLee
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701ba16491
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cleanup
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2023-10-24 15:34:30 +08:00 |
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RuigeLee
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86fb086bd2
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tx 32转8 基本测试通过
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2023-10-24 14:00:51 +08:00 |
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RuigeLee
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54991d8cb5
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Tx尝试统一接口，失败
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2023-10-23 23:36:01 +08:00 |
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RuigeLee
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faa46be8ef
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Rx的req resp跨时钟架构
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2023-10-23 22:58:36 +08:00 |
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RuigeLee
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bf66bae475
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rx 通道基本完成32转8，存在跨时钟域风险
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2023-10-21 21:08:40 +08:00 |
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RuigeLee
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69ccc32603
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在32数据通道下传输正确
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2023-10-20 20:56:44 +08:00 |
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RuigeLee
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f17d405369
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Rx DMA 传输正确
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2023-10-20 15:49:24 +08:00 |
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RuigeLee
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0215add0d4
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rx DMA编译完成
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2023-10-20 14:42:15 +08:00 |
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RuigeLee
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c5f9b4d74f
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未完成，尝试建立DMA
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2023-10-19 18:31:26 +08:00 |
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RuigeLee
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70922ecb44
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拓扑修改，编译通过
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2023-10-19 15:24:26 +08:00 |
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RuigeLee
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d77c69aa5a
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接收数据流解耦初步测试成功
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2023-10-18 17:11:56 +08:00 |
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RuigeLee
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629d9486d1
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完成编译，准备接入CPU查看信号逻辑
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2023-10-17 16:38:18 +08:00 |
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RuigeLee
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7c71c005f8
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基本清理完成
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2023-10-14 12:36:37 +08:00 |
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RuigeLee
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0c60fbfb15
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未完成清理tx，txready初始化为true
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2023-10-13 18:18:02 +08:00 |
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RuigeLee
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ceef60b95c
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断言不会发生tx Underrun
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2023-10-13 15:21:53 +08:00 |
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