Ruige Lee
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6d8edfd6ce
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锁定后，每16个cycle ，或许有bug
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2025-08-20 19:08:51 +08:00 |
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Ruige Lee
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0291d445ca
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Revert "cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁"
This reverts commit d7146a786b.
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2025-08-20 15:40:25 +08:00 |
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Ruige Lee
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d7146a786b
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cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
需要配平fifo，覆盖每个长度端，长度边缘，解锁在crc位置，不同preamble长度
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2025-08-19 17:04:58 +08:00 |
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Ruige Lee
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f3916df37b
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弃用高频率采样CDR的例化
Merge branch 'mp_eb_dev_多采样全表决' into mp_eb_dev
* mp_eb_dev_多采样全表决:
调整解锁条件为10个连续0
增加一个锁定可以暂时解决发送失败问题
滤波 表决 鉴相同时存在
enhance 要求先跨时钟，再进行后续表决
Revert "16相位改8相位"
16相位改8相位
bug: 16相位补充相 欠了一相
Revert "改6相位，从一个pll出，测试"
Revert "尝试3相位"
尝试3相位
改6相位，从一个pll出，测试
拉出测试IO
Revert "4多相位效果明显更好"
4多相位效果明显更好
16相位操作还是卡
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-19 10:00:25 +08:00 |
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Ruige Lee
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2fb450673f
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调整解锁条件为10个连续0
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2025-08-18 17:39:32 +08:00 |
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Ruige Lee
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2afd3f722a
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增加一个锁定可以暂时解决发送失败问题
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2025-08-18 16:20:50 +08:00 |
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Ruige Lee
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11bbf14226
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滤波 表决 鉴相同时存在
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2025-08-15 17:18:45 +08:00 |
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Ruige Lee
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45d2d223c1
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enhance 要求先跨时钟，再进行后续表决
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2025-08-15 15:28:28 +08:00 |
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Ruige Lee
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62684bd665
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Revert "16相位改8相位"
This reverts commit 2da45138db.
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2025-08-15 10:45:44 +08:00 |
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Ruige Lee
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2da45138db
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16相位改8相位
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2025-08-15 10:45:10 +08:00 |
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Ruige Lee
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fc917054ed
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bug: 16相位补充相 欠了一相
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2025-08-14 19:23:56 +08:00 |
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Ruige Lee
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573a1ad45f
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bug:滤波需要顺序打拍，防止边界上跳变
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2025-08-14 19:15:09 +08:00 |
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Ruige Lee
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035109bee1
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Revert "改6相位，从一个pll出，测试"
This reverts commit 495a238a26.
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2025-08-13 17:54:50 +08:00 |
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Ruige Lee
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4955b7a278
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Revert "尝试3相位"
This reverts commit c6aa7416fc.
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2025-08-13 17:54:39 +08:00 |
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Ruige Lee
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c6aa7416fc
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尝试3相位
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2025-08-13 10:52:49 +08:00 |
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Ruige Lee
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495a238a26
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改6相位，从一个pll出，测试
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2025-08-13 10:00:11 +08:00 |
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Ruige Lee
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cb2c4f46e5
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拉出测试IO
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2025-08-12 17:48:35 +08:00 |
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Ruige Lee
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107895f6e0
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Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
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2025-08-12 09:55:43 +08:00 |
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Ruige Lee
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7338314c17
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4多相位效果明显更好
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2025-08-11 19:33:56 +08:00 |
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Ruige Lee
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b0b221e8b0
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16相位操作还是卡
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2025-08-11 18:13:58 +08:00 |
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Ruige Lee
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1cb0cee966
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should >= 3
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2025-08-11 10:07:54 +08:00 |
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Ruige Lee
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a31b08dcda
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDROut.scala
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2025-08-11 10:07:18 +08:00 |
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Ruige Lee
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cae503f4c2
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preamble应该大于3
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2025-08-11 10:05:49 +08:00 |
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RuigeLee
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424e07a076
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增加5选3多数表决滤波
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2025-08-09 22:22:19 +08:00 |
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1ce3840567
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PRE_NUM改为8后，功能正常
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2025-08-08 22:42:21 +08:00 |
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Ruige Lee
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dc4539124c
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可调preamble长度
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2025-08-07 17:39:11 +08:00 |
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Ruige Lee
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8c09a6c4aa
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写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
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2025-08-05 16:49:41 +08:00 |
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656986a8ab
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:Merge branch 'feature_shintop' into eb_dev
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2025-07-30 23:14:37 +08:00 |
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Ruige Lee
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8ba8ff0e9e
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**抹除**加密特性
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2025-07-30 15:36:18 +08:00 |
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Ruige Lee
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302893c3e7
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加入CDR的滤波，并修改测试led
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2025-07-28 14:31:45 +08:00 |
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Ruige Lee
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9f88d26ba1
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多相位时钟可以使用
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2025-07-22 11:49:33 +08:00 |
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Ruige Lee
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7c632c8c1b
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编译通过
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2025-07-22 09:35:06 +08:00 |
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Ruige Lee
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bf8fce2671
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需要考虑多项位时钟是按同步时钟还是异步时钟处理
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2025-07-17 17:47:59 +08:00 |
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Ruige Lee
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1319027c9e
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代码清理
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2025-07-17 17:22:08 +08:00 |
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Ruige Lee
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581c614017
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撤销idle状态cdrout强制传输线为0的设定
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2025-07-17 10:03:31 +08:00 |
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Ruige Lee
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cea2d01945
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使用rec的清中断复位sendGen模块；当CDRout的axis下溢，状态机回到IDLE
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2025-07-15 16:30:44 +08:00 |
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Ruige Lee
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370e6b119c
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处理断言及状态机卡住问题，从这个版本开始，所有断言错误都应该处理；recParser的错误状态会触发5、6号不可屏蔽中断，软件需要清中断然后recParser恢复状态，cdrout溢出问题不再触发中断，该次传输将会发生至少两次错误
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2025-05-26 11:52:40 +08:00 |
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Ruige Lee
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a4515146f7
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加密特性长度修复
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2025-05-22 17:28:31 +08:00 |
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Ruige Lee
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8f59ef55ac
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加密模块
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2025-05-22 16:54:17 +08:00 |
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Ruige Lee
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944255978a
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增加加密特性（未测试）
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2025-05-22 16:53:42 +08:00 |
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Ruige Lee
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4b2a52fa9b
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转发延迟缩减至126个cycle
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2025-05-20 11:35:11 +08:00 |
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Ruige Lee
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fb8bc91947
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暂时改回4倍采样以实现FPGA逻辑
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2025-05-13 17:05:38 +08:00 |
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Ruige Lee
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b55deb239f
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尝试速率配平，回环改到phy上
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2025-05-07 18:12:01 +08:00 |
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Ruige Lee
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19f4140dec
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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
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2025-05-06 17:39:52 +08:00 |
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Ruige Lee
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dabfc86983
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发送单元 接收单元代码收尾
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2025-04-09 17:29:57 +08:00 |
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Ruige Lee
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6c6cce1222
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CDRIn采样率改为8x，允许参数化
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2025-04-02 15:44:32 +08:00 |
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Ruige Lee
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bcb1c8e8f3
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修改指令编号
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2025-03-04 14:45:31 +08:00 |
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Ruige Lee
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46cbd6edec
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rxFifo bypass to txFifo
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2025-03-04 12:01:47 +08:00 |
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Ruige Lee
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1c7eb4ce47
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使用未使用4b/5b编码作为preamble
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2025-03-04 10:58:59 +08:00 |
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Ruige Lee
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9937485831
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bug修复：定义CDR清中断和中断到来同时发生的行为
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2025-02-27 17:27:15 +08:00 |
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