RuigeLee
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2048a4d286
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first test
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2023-07-28 15:38:46 +08:00 |
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Ruige
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85fe9175e6
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backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
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2023-07-25 21:05:43 +08:00 |
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RuigeLee
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21f8547273
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ethreg Test pass
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2023-07-21 16:38:02 +08:00 |
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RuigeLee
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0b48e2cd2b
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compile pass
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2023-07-20 14:58:59 +08:00 |
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RuigeLee
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02ec89bda5
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axi opt
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2023-07-12 18:43:28 +08:00 |
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RuigeLee
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63be80135c
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tl to axi in single device
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2023-07-12 17:24:42 +08:00 |
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RuigeLee
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8b2121959e
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中断节点化
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2023-07-11 22:02:41 +08:00 |
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RuigeLee
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2d720b7c8d
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remove istilelink parameter
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2023-07-11 17:45:32 +08:00 |
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RuigeLee
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44048ea7d9
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remove all wishbone
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2023-07-11 17:38:18 +08:00 |
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RuigeLee
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3037d31028
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move tlsram to chisel
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2023-07-11 00:00:26 +08:00 |
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RuigeLee
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0303ca21fb
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top layer and some bugs fixed
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2023-07-03 23:51:01 +08:00 |
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RuigeLee
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61e36c59d8
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wishbone test pass
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2023-06-29 18:29:54 +08:00 |
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RuigeLee
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9e3786785c
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macregister
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2023-06-26 21:55:20 +08:00 |
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RuigeLee
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0fc0325969
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pass tx rx status ctrl
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2023-06-25 22:53:44 +08:00 |
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RuigeLee
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505aa7326a
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finish macrx
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2023-06-21 21:55:16 +08:00 |
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RuigeLee
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ac7db49089
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compare test pass
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2023-06-20 18:26:59 +08:00 |
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e84986160f
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Initial commit
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2023-06-18 12:41:33 +08:00 |
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