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0c9c52a57a
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修复主分支下的multiclk产生的错误
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2025-09-01 16:31:27 +08:00 |
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08f602ab1b
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合并通讯线路的交叉功能,为环网做准备
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2025-09-01 16:18:25 +08:00 |
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b8da95422e
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修改测试用例, 80ppm通过
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2025-09-01 16:12:37 +08:00 |
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a5919e29c0
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增加测试用例29
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2025-08-30 14:55:25 +08:00 |
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0bb9f89969
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修正测试用例
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2025-08-30 14:54:10 +08:00 |
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25577a4d50
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增加测试代码
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2025-08-30 14:32:05 +08:00 |
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0bcb947a2d
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增加线路交叉的测试用例
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2025-08-30 13:04:17 +08:00 |
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17a6f5a3f8
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增加测试用例
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2025-08-29 17:20:40 +08:00 |
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e9d412561e
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增加频率差160ppm的测试代码
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2025-08-29 16:45:11 +08:00 |
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Ruige Lee
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60eec33b2d
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上下行交换特性
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2025-08-29 15:37:29 +08:00 |
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Ruige Lee
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51d29f1dd7
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Merge branch 'mp_eb_dev' into feature/dwupEx
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2025-08-29 11:12:53 +08:00 |
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Ruige Lee
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1a01fa9d72
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CDR仿真文件
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2025-08-28 20:06:14 +08:00 |
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Ruige Lee
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08f74c6986
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Merge branch 'feature/cdrSim' into mp_eb_dev
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2025-08-28 20:04:30 +08:00 |
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Ruige Lee
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bbfc0322e9
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增加CDR仿真例程
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2025-08-28 20:03:42 +08:00 |
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Ruige Lee
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55ea876488
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同上
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2025-08-28 16:10:57 +08:00 |
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Ruige Lee
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659ab14fab
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修改同步点调整逻辑
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2025-08-28 15:53:17 +08:00 |
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Ruige Lee
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d4c793bf0b
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修正同步宽度不能spi修改的问题
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2025-08-28 11:07:57 +08:00 |
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6d6e07346b
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增加主站的同步输出
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2025-08-28 10:49:58 +08:00 |
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Ruige Lee
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f5336f1dc5
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硬件错误中断捕捉边缘
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2025-08-28 10:28:59 +08:00 |
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4979a10a72
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配置测试环境
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2025-08-28 10:16:55 +08:00 |
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39a3f01936
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增加测试用例
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2025-08-28 09:59:15 +08:00 |
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Ruige Lee
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706b9f17e5
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FPGA测试通过
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2025-08-27 17:06:31 +08:00 |
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Ruige Lee
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e44373ab83
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校准时间
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2025-08-27 16:31:17 +08:00 |
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Ruige Lee
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58ad17ce79
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修复
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2025-08-27 16:27:00 +08:00 |
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Ruige Lee
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a09ccef57f
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缩短主从同步时间差
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2025-08-27 16:05:20 +08:00 |
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Ruige Lee
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9773752cc8
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上下行交换特性
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2025-08-27 15:55:09 +08:00 |
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Ruige Lee
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fa3ba57f32
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spi写pll寄存器信号拉到顶层
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2025-08-27 15:20:43 +08:00 |
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Ruige Lee
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bdabf08108
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Merge branch 'mp_eb_dev' into feature/clk3_shift_allow
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-27 14:59:39 +08:00 |
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Ruige Lee
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dd71c557b7
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Merge branch 'feature/liftCdr' into mp_eb_dev
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2025-08-27 14:45:29 +08:00 |
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Ruige Lee
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4e2e3f6ca4
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修复sync的64位加法器输入位宽转换问题
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2025-08-27 09:42:01 +08:00 |
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c69acb4bf0
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sync不能工作,已确认,需要检查代码
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2025-08-26 20:35:21 +08:00 |
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Ruige Lee
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4b90a2c9bd
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CDR拉到顶层
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2025-08-26 17:52:23 +08:00 |
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1fe1959f8c
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增加新的测试用例,测试sync寄存器组的时间读取,以免发生进位错误
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2025-08-26 17:35:46 +08:00 |
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f8065c79c9
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修正基础库里生成代码的方式，删除不必要的废代码
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2025-08-26 17:35:46 +08:00 |
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Ruige Lee
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c6bd7902e7
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Merge branch 'mp_eb_dev' into feature/liftCdr
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2025-08-26 17:07:58 +08:00 |
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Ruige Lee
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b821571218
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同步逻辑扩展delta位宽，使用分时共享64位加法器
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2025-08-26 17:02:57 +08:00 |
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Ruige Lee
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ae99f5801d
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spi读锁定0x118
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2025-08-26 15:17:37 +08:00 |
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Ruige Lee
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6b118fa498
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spi读0x100将会暂存后续寄存器防止进位
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2025-08-26 11:35:47 +08:00 |
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Ruige Lee
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72fe230200
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尝试把CDR提到顶层
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2025-08-26 10:30:12 +08:00 |
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Ruige Lee
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249a94a64b
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-08-25 19:17:08 +08:00 |
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Ruige Lee
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6f1101f6dc
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改异步复位，增加flush接口，删除其他工程代码以编译通过
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2025-08-25 19:16:27 +08:00 |
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79f29a1d7e
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修正自动添加从站设备的测试用例
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2025-08-25 17:50:01 +08:00 |
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Ruige Lee
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7dd8458f96
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允许正负3个cycle偏移
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2025-08-25 17:32:21 +08:00 |
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Ruige Lee
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bca9724c3c
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修改pllctrl复位默认值
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2025-08-25 14:30:15 +08:00 |
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Ruige Lee
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976c468b6a
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修改pllctrl复位默认值
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2025-08-25 11:41:53 +08:00 |
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Ruige Lee
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800592c646
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CDRIn相位校准
Merge branch 'feature/auto_release_insert' into mp_eb_dev
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2025-08-25 11:04:22 +08:00 |
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b7f5fe5749
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1.增加测试用例；2.增加自动生成从站数量的代码，可更改成任意的从站数量
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2025-08-25 00:32:52 +08:00 |
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1ea82ab72c
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降低采样缓冲区的数据缓冲量
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2025-08-24 17:58:22 +08:00 |
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7a54581b91
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增加CDR仿真下不同采样频率的代码
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2025-08-24 16:53:35 +08:00 |
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dc67fee68e
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增加新的测试用例,仿真实际中的情况
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2025-08-22 18:07:17 +08:00 |
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