From ffb4db197d6ce068c2052d90f33779baefa41418 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Mon, 2 Feb 2026 09:37:53 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8Dsspi=E8=AF=BB=E4=B8=A2?=
 =?UTF-8?q?=E5=A4=B1=E7=AC=AC=E4=B8=80byte=E7=9A=84=E9=97=AE=E9=A2=98?=
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---
 src/main/scala/backBoard/shin/SpiInterface.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index bc43850..8408789 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -156,7 +156,7 @@ class SSpiInterface extends SpiInterfaceBase{
     exRego := 0.U //第一个byte 地址0
   } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
     when( bitSel.andR ){
-      when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || byteSel === 3.U ) ){
+      when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U ) ){ //第3byte准备，第4byte开始发送
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
         exRego := io.datar