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Ruige Lee (WSL)
2025-01-11 14:50:27 +08:00
parent 05162537b6
commit fef7acb54a
3 changed files with 45 additions and 58 deletions
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5
Makefile
View File

@@ -53,13 +53,14 @@ VSimTop:
test: test:
./tb/build/VSimTop -w -l -f ./tb/sw/build/test ./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest
sw: sw:
rm ./tb/sw/build/* -f rm ./tb/sw/build/* -f
mkdir -p ./tb/sw/build/
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \ -I ./tb/sw/ -I ./tb/sw/src \
@@ -83,7 +84,7 @@ sw:
-o ./tb/sw/build/mstTest.elf -o ./tb/sw/build/mstTest.elf
riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog

92
tb/verilator/SimTop.v
View File

@@ -2,23 +2,6 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
@@ -147,13 +130,13 @@ ExampleRocketSystem s_rocket(
reg [1023:0] firmware_file; // reg [1023:0] firmware_file;
initial begin // initial begin
if ($value$plusargs("%s", firmware_file)) begin // if ($value$plusargs("%s", firmware_file)) begin
$display("%s", firmware_file); // $display("%s", firmware_file);
$readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram); // $readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
end // end
end // end
@@ -167,44 +150,47 @@ ExampleRocketSystem s_rocket(
// string testName; string testName;
// `define MEM s_axi_full_slv_sram.i_sram.ram `define MEM s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram
// reg [7:0] mem [0:200000]; reg [7:0] mem [0:200000];
// localparam DP = 2**18; localparam DP = 8192;
// integer i, by; integer i;
// initial begin initial begin
// #20 #20
// if ( $value$plusargs("%s",testName) ) begin if ( $value$plusargs("%s",testName) ) begin
// $display("%s",testName); $display("%s",testName);
// $readmemh(testName, mem); $readmemh(testName, mem);
end
// end else begin
// else begin $display("%s",testName);
// $display("%s",testName); $error("Failed to read Files!");
// $error("Failed to read Files!"); end
// end
// for ( i = 0; i < DP; i = i + 1 ) begin for ( i = 0; i < DP; i = i + 1 ) begin
// for ( by = 0; by < 4; by = by + 1 ) begin if ( mem[i*4+0] || mem[i*4+1] || mem[i*4+2] || mem[i*4+3] ) begin
// if ( | mem[i*4+by] ) begin `MEM[i] = {mem[i*4+3], mem[i*4+2], mem[i*4+1], mem[i*4+0]};
// `MEM[i][8*by +: 8] = mem[i*4+by];
// end
// else begin
// `MEM[i][8*by +: 8] = 8'h0;
// end
// end
// end
$display("%x",`MEM[i]);
end
else begin
`MEM[i][7:0] = 8'h0;
`MEM[i][15:8] = 8'h0;
`MEM[i][23:16] = 8'h0;
`MEM[i][31:24] = 8'h0;
end
end
end
// end wire [31:0] test1 = `MEM[0];
wire [31:0] test2 = `MEM[1];
wire [31:0] test3 = `MEM[2];
wire [31:0] test4 = `MEM[3];

6
tb/verilator/sim_main.cpp
View File

@@ -102,7 +102,7 @@ int main(int argc, char **argv, char **env) {
char * temp[2]; char * temp[2];
char cmd[64] = "+"; char cmd[64] = "+";
strcat(cmd, img); strcat(cmd, img);
// strcat(cmd, ".hex"); strcat(cmd, ".verilog");
temp[0] = "Verilated"; temp[0] = "Verilated";
temp[1] = cmd; temp[1] = cmd;
char **argv_temp = temp; char **argv_temp = temp;
@@ -118,7 +118,7 @@ int main(int argc, char **argv, char **env) {
Verilated::traceEverOn(true); Verilated::traceEverOn(true);
top->trace(tfp, 99); // Trace 99 levels of hierarchy top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("./build/wave.fst"); tfp->open("./tb/build/wave.fst");
} }
#endif #endif
@@ -140,7 +140,7 @@ int main(int argc, char **argv, char **env) {
#endif #endif
if ( flag_limitEnable ) { if ( flag_limitEnable ) {
if ( main_cycle > 300000 ){ if ( main_cycle > 3000 ){
std::cout << "Timeout!!!!!" << std::endl; std::cout << "Timeout!!!!!" << std::endl;
sim_exit(); sim_exit();
return -1; return -1;