compile and realign pass
This commit is contained in:
RuigeLee
@@ -85,16 +85,7 @@ class MacImp(outer: Mac) extends LazyModuleImp(outer){
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//( if(!isTileLink) { IO(new MacIO with MDIO with MacWishboneMasterIO with MacWishboneSlaveIO) } //else {IO(new MacIO with MDIO with MacWishboneMasterIO)} )
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val m_wb_adr_tmp = Wire(UInt(30.W))
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val wb_dbg_dat0 = Wire(UInt(32.W))
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val m_wb_adr_tmp = Wire(UInt(30.W))
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val r_ClkDiv = Wire(UInt(8.W))
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val r_MiiNoPre = Wire(Bool())
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val r_CtrlData = Wire(UInt(16.W))
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@@ -111,22 +102,52 @@ val WCtrlDataStart = Wire(Bool())
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val RStatStart = Wire(Bool())
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val UpdateMIIRX_DATAReg = Wire(Bool())
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dontTouch( m_wb_adr_tmp )
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dontTouch( r_ClkDiv )
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dontTouch( r_MiiNoPre )
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dontTouch( r_CtrlData )
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dontTouch( r_FIAD )
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dontTouch( r_RGAD )
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dontTouch( r_WCtrlData )
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dontTouch( r_RStat )
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dontTouch( r_ScanStat )
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dontTouch( NValid_stat )
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dontTouch( Busy_stat )
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dontTouch( LinkFail )
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dontTouch( Prsd )
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dontTouch( WCtrlDataStart )
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dontTouch( RStatStart )
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dontTouch( UpdateMIIRX_DATAReg )
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val TxStartFrm = Wire(Bool())
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val TxEndFrm = Wire(Bool())
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val TxEndFrm = Wire(Bool())
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val TxUsedData = Wire(Bool())
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val TxData = Wire(UInt(8.W))
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val TxRetry = Wire(Bool())
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val TxAbort = Wire(Bool())
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val TxData = Wire(UInt(8.W))
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val TxRetry = Wire(Bool())
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val TxAbort = Wire(Bool())
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val TxUnderRun = Wire(Bool())
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val TxDone = Wire(Bool())
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val RstTxPauseRq = RegInit(Bool())
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val TxDone = Wire(Bool())
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val TPauseRq = Wire(Bool())
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dontTouch(TxStartFrm)
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dontTouch(TxEndFrm )
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dontTouch(TxUsedData)
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dontTouch(TxData )
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dontTouch(TxRetry )
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dontTouch(TxAbort )
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dontTouch(TxUnderRun)
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dontTouch(TxDone )
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dontTouch(TPauseRq )
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val RstTxPauseRq = RegInit(false.B)
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// Connecting Miim module
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val miim = Module(new MIIM)
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@@ -164,83 +185,146 @@ val miim = Module(new MIIM)
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val RegDataOut = Wire(UInt(32.W))
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val r_RecSmall = Wire(Bool())
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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val r_RxEn = Wire(Bool())
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val MRxDV_Lb = Wire(Bool())
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val MRxErr_Lb = Wire(Bool())
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val MRxD_Lb = Wire(UInt(4.W))
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val Transmitting = Wire(Bool())
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val r_HugEn = Wire(Bool())
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val r_DlyCrcEn = Wire(Bool())
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val r_MaxFL = Wire(UInt(16.W))
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val r_MinFL = Wire(UInt(16.W))
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val ShortFrame = Wire(Bool())
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val DribbleNibble = Wire(Bool())
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val ReceivedPacketTooBig = Wire(Bool())
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val r_MAC = Wire(UInt(48.W))
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val LoadRxStatus = Wire(Bool())
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val r_HASH0 = Wire(UInt(32.W))
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val r_HASH1 = Wire(UInt(32.W))
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val r_TxBDNum = Wire(UInt(8.W))
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val r_IPGT = Wire(UInt(7.W))
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val r_IPGR1 = Wire(UInt(7.W))
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val r_IPGR2 = Wire(UInt(7.W))
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val r_CollValid = Wire(UInt(6.W))
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val r_TxPauseTV = Wire(UInt(16.W))
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val r_TxPauseRq = Wire(Bool())
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val r_MaxRet = Wire(UInt(4.W))
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val r_NoBckof = Wire(Bool())
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val r_ExDfrEn = Wire(Bool())
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val r_TxFlow = Wire(Bool())
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val r_IFG = Wire(Bool())
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val TxB_IRQ = Wire(Bool())
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val TxE_IRQ = Wire(Bool())
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val RxB_IRQ = Wire(Bool())
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val RxE_IRQ = Wire(Bool())
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val Busy_IRQ = Wire(Bool())
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val r_Pad = Wire(Bool())
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val r_CrcEn = Wire(Bool())
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val r_FullD = Wire(Bool())
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val r_Pro = Wire(Bool())
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val r_Bro = Wire(Bool())
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val r_NoPre = Wire(Bool())
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val r_RxFlow = Wire(Bool())
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val r_PassAll = Wire(Bool())
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val TxCtrlEndFrm = Wire(Bool())
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val StartTxDone = Wire(Bool())
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val SetPauseTimer = Wire(Bool())
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val TxUsedDataIn = Wire(Bool())
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val TxDoneIn = Wire(Bool())
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val TxAbortIn = Wire(Bool())
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val PerPacketPad = Wire(Bool())
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val PadOut = Wire(Bool())
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val PerPacketCrcEn = Wire(Bool())
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val CrcEnOut = Wire(Bool())
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val TxStartFrmOut = Wire(Bool())
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val TxEndFrmOut = Wire(Bool())
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val ReceivedPauseFrm = Wire(Bool())
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val ControlFrmAddressOK = Wire(Bool())
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val RegDataOut = Wire(UInt(32.W))
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val r_RecSmall = Wire(Bool())
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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val r_RxEn = Wire(Bool())
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val MRxDV_Lb = Wire(Bool())
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val MRxErr_Lb = Wire(Bool())
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val MRxD_Lb = Wire(UInt(4.W))
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val Transmitting = Wire(Bool())
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val r_HugEn = Wire(Bool())
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val r_DlyCrcEn = Wire(Bool())
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val r_MaxFL = Wire(UInt(16.W))
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val r_MinFL = Wire(UInt(16.W))
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val ShortFrame = Wire(Bool())
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val DribbleNibble = Wire(Bool())
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val ReceivedPacketTooBig = Wire(Bool())
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val r_MAC = Wire(UInt(48.W))
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val LoadRxStatus = Wire(Bool())
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val r_HASH0 = Wire(UInt(32.W))
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val r_HASH1 = Wire(UInt(32.W))
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val r_TxBDNum = Wire(UInt(8.W))
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val r_IPGT = Wire(UInt(7.W))
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val r_IPGR1 = Wire(UInt(7.W))
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val r_IPGR2 = Wire(UInt(7.W))
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val r_CollValid = Wire(UInt(6.W))
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val r_TxPauseTV = Wire(UInt(16.W))
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val r_TxPauseRq = Wire(Bool())
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val r_MaxRet = Wire(UInt(4.W))
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val r_NoBckof = Wire(Bool())
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val r_ExDfrEn = Wire(Bool())
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val r_TxFlow = Wire(Bool())
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val r_IFG = Wire(Bool())
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val TxB_IRQ = Wire(Bool())
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val TxE_IRQ = Wire(Bool())
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val RxB_IRQ = Wire(Bool())
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val RxE_IRQ = Wire(Bool())
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val Busy_IRQ = Wire(Bool())
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val r_Pad = Wire(Bool())
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val r_CrcEn = Wire(Bool())
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val r_FullD = Wire(Bool())
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val r_Pro = Wire(Bool())
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val r_Bro = Wire(Bool())
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val r_NoPre = Wire(Bool())
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val r_RxFlow = Wire(Bool())
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val r_PassAll = Wire(Bool())
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val TxCtrlEndFrm = Wire(Bool())
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val StartTxDone = Wire(Bool())
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val SetPauseTimer = Wire(Bool())
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val TxUsedDataIn = Wire(Bool())
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val TxDoneIn = Wire(Bool())
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val TxAbortIn = Wire(Bool())
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val PerPacketPad = Wire(Bool())
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val PadOut = Wire(Bool())
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val PerPacketCrcEn = Wire(Bool())
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val CrcEnOut = Wire(Bool())
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val TxStartFrmOut = Wire(Bool())
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val TxEndFrmOut = Wire(Bool())
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val ReceivedPauseFrm = Wire(Bool())
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val ControlFrmAddressOK = Wire(Bool())
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val RxStatusWriteLatched_sync2 = Wire(Bool())
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val LateCollision = Wire(Bool())
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val DeferIndication = Wire(Bool())
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val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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val LateCollision = Wire(Bool())
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val DeferIndication = Wire(Bool())
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val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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val RegCs = Wire(UInt(4.W))
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dontTouch(RegDataOut )
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dontTouch(r_RecSmall )
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dontTouch(r_LoopBck )
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dontTouch(r_TxEn )
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dontTouch(r_RxEn )
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dontTouch(MRxDV_Lb )
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dontTouch(MRxErr_Lb )
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dontTouch(MRxD_Lb )
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dontTouch(Transmitting )
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dontTouch(r_HugEn )
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dontTouch(r_DlyCrcEn )
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dontTouch(r_MaxFL )
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dontTouch(r_MinFL )
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dontTouch(ShortFrame )
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dontTouch(DribbleNibble )
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dontTouch(ReceivedPacketTooBig )
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dontTouch(r_MAC )
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dontTouch(LoadRxStatus )
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dontTouch(r_HASH0 )
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dontTouch(r_HASH1 )
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dontTouch(r_TxBDNum )
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dontTouch(r_IPGT )
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dontTouch(r_IPGR1 )
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dontTouch(r_IPGR2 )
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dontTouch(r_CollValid )
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dontTouch(r_TxPauseTV )
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dontTouch(r_TxPauseRq )
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dontTouch(r_MaxRet )
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dontTouch(r_NoBckof )
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dontTouch(r_ExDfrEn )
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dontTouch(r_TxFlow )
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dontTouch(r_IFG )
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dontTouch(TxB_IRQ )
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dontTouch(TxE_IRQ )
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dontTouch(RxB_IRQ )
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dontTouch(RxE_IRQ )
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dontTouch(Busy_IRQ )
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dontTouch(r_Pad )
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dontTouch(r_CrcEn )
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dontTouch(r_FullD )
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dontTouch(r_Pro )
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dontTouch(r_Bro )
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dontTouch(r_NoPre )
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dontTouch(r_RxFlow )
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dontTouch(r_PassAll )
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dontTouch(TxCtrlEndFrm )
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dontTouch(StartTxDone )
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dontTouch(SetPauseTimer )
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dontTouch(TxUsedDataIn )
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dontTouch(TxDoneIn )
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dontTouch(TxAbortIn )
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dontTouch(PerPacketPad )
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dontTouch(PadOut )
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dontTouch(PerPacketCrcEn )
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dontTouch(CrcEnOut )
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dontTouch(TxStartFrmOut )
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dontTouch(TxEndFrmOut )
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dontTouch(ReceivedPauseFrm )
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dontTouch(ControlFrmAddressOK )
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dontTouch(RxStatusWriteLatched_sync2 )
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dontTouch(LateCollision )
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dontTouch(DeferIndication )
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dontTouch(LateCollLatched )
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dontTouch(DeferLatched )
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dontTouch(RstDeferLatched )
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dontTouch(CarrierSenseLost )
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dontTouch(RegCs )
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val RegCs = Wire(UInt(4.W))
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val ethReg = Module(new MacReg)
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@@ -267,7 +351,7 @@ ethReg.io.StartTxDone := StartTxDone
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ethReg.io.TxClk := io.mtx_clk_pad_i
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ethReg.io.RxClk := io.mrx_clk_pad_i
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ethReg.io.SetPauseTimer := SetPauseTimer
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ethReg.io.dbg_dat := wb_dbg_dat0
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ethReg.io.dbg_dat := 0.U
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RegDataOut := ethReg.io.DataOut
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r_RecSmall := ethReg.io.r_RecSmall
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@@ -314,29 +398,52 @@ r_TxPauseRq := ethReg.io.r_TxPauseRq
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val RxData = Wire(UInt(8.W))
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val RxValid = Wire(Bool())
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val RxStartFrm = Wire(Bool())
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val RxEndFrm = Wire(Bool())
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val RxAbort = Wire(Bool())
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val WillTransmit = Wire(Bool())
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val ResetCollision = Wire(Bool())
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val TxDataOut = Wire(UInt(8.W))
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val RxData = Wire(UInt(8.W))
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val RxValid = Wire(Bool())
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val RxStartFrm = Wire(Bool())
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val RxEndFrm = Wire(Bool())
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val RxAbort = Wire(Bool())
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val WillTransmit = Wire(Bool())
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val ResetCollision = Wire(Bool())
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val TxDataOut = Wire(UInt(8.W))
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val WillSendControlFrame = Wire(Bool())
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val ReceiveEnd = Wire(Bool())
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val ReceivedPacketGood = Wire(Bool())
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val ReceivedLengthOK = Wire(Bool())
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val InvalidSymbol = Wire(Bool())
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val LatchedCrcError = Wire(Bool())
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val RxLateCollision = Wire(Bool())
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val RetryCntLatched = Wire(UInt(4.W))
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val RetryCnt = Wire(UInt(4.W))
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val StartTxAbort = Wire(Bool())
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val MaxCollisionOccured = Wire(Bool())
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val RetryLimit = Wire(Bool())
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val StatePreamble = Wire(Bool())
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val StateData = Wire(UInt(2.W))
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val ReceiveEnd = Wire(Bool())
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val ReceivedPacketGood = Wire(Bool())
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val ReceivedLengthOK = Wire(Bool())
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val InvalidSymbol = Wire(Bool())
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val LatchedCrcError = Wire(Bool())
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val RxLateCollision = Wire(Bool())
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val RetryCntLatched = Wire(UInt(4.W))
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val RetryCnt = Wire(UInt(4.W))
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val StartTxAbort = Wire(Bool())
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val MaxCollisionOccured = Wire(Bool())
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val RetryLimit = Wire(Bool())
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val StatePreamble = Wire(Bool())
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val StateData = Wire(UInt(2.W))
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dontTouch(RxData )
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dontTouch(RxValid )
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dontTouch(RxStartFrm )
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dontTouch(RxEndFrm )
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dontTouch(RxAbort )
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dontTouch(WillTransmit )
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dontTouch(ResetCollision )
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dontTouch(TxDataOut )
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dontTouch(WillSendControlFrame)
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dontTouch(ReceiveEnd )
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dontTouch(ReceivedPacketGood )
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dontTouch(ReceivedLengthOK )
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dontTouch(InvalidSymbol )
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dontTouch(LatchedCrcError )
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dontTouch(RxLateCollision )
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dontTouch(RetryCntLatched )
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dontTouch(RetryCnt )
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dontTouch(StartTxAbort )
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dontTouch(MaxCollisionOccured )
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dontTouch(RetryLimit )
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dontTouch(StatePreamble )
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dontTouch(StateData )
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// Connecting MACControl
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val maccontrol = Module(new MacControl)
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@@ -388,16 +495,15 @@ SetPauseTimer := maccontrol.io.SetPauseTimer
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val TxCarrierSense = Wire(Bool())
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val Collision = Wire(Bool())
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val TxCarrierSense = Wire(Bool())
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val Collision = Wire(Bool())
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val CarrierSense_Tx2 = Wire(Bool())
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val RxEnSync = Wire(Bool())
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val RxEnSync = Wire(Bool())
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dontTouch(TxCarrierSense )
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dontTouch(Collision )
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dontTouch(CarrierSense_Tx2)
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dontTouch(RxEnSync )
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// Muxed MII receive data valid
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@@ -411,7 +517,7 @@ MRxD_Lb := Mux(r_LoopBck, io.mtxd_pad_o, io.mrxd_pad_i)
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val txethmac = Module(new MacTx)
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txethmac.clock := io.mtx_clk_pad_i
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txethmac.clock := io.mtx_clk_pad_i.asClock
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txethmac.reset := reset.asBool
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txethmac.io.TxStartFrm := TxStartFrmOut
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txethmac.io.TxEndFrm := TxEndFrmOut
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@@ -468,8 +574,19 @@ val RxStateData = Wire(UInt(2.W))
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val AddressMiss = Wire(Bool())
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dontTouch(RxByteCnt )
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dontTouch(RxByteCntEq0 )
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dontTouch(RxByteCntGreat2 )
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dontTouch(RxByteCntMaxFrame)
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dontTouch(RxCrcError )
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dontTouch(RxStateIdle )
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dontTouch(RxStatePreamble )
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dontTouch(RxStateSFD )
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dontTouch(RxStateData )
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dontTouch(AddressMiss )
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val rxethmac = Module(new MacRx)
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rxethmac.clock := io.mrx_clk_pad_i
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rxethmac.clock := io.mrx_clk_pad_i.asClock
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rxethmac.reset := reset.asBool
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rxethmac.io.MRxDV := MRxDV_Lb
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rxethmac.io.MRxD := MRxD_Lb
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@@ -560,7 +677,7 @@ val rxethmac = Module(new MacRx)
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val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
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withClockAndReset( io.mrx_clk_pad_i.asClock, reset ) {
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val RxAbort_latch = RegInit(false.B)
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val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
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val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
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// Synchronizing RxAbort to the WISHBONE clock
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Reference in New Issue
Block a user