diff --git a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala b/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
index 20b954f..10179ea 100644
--- a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
+++ b/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
@@ -164,8 +164,8 @@ class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
     // val tld = Wire(new DecoupledIO(new TLBundleD(fsmc_edge.bundle)))
 
     val sram  = Module(new MirrorSRAMDP())
-    assert( ~(sram.io.enwA & sram.io.enrA) )
-    assert( ~(sram.io.enwB & sram.io.enrB) )
+    //assert( ~(sram.io.enwA & sram.io.enrA) )
+    //assert( ~(sram.io.enwB & sram.io.enrB) )
     sram.io.clockA := clock.asBool //system
     sram.io.clockB := clock.asBool //system
 
diff --git a/tb/sw/src/MstMain.c b/tb/sw/src/MstMain.c
index e60f97f..93264b7 100644
--- a/tb/sw/src/MstMain.c
+++ b/tb/sw/src/MstMain.c
@@ -117,7 +117,7 @@ void main()
 	
 	tx_len = 32;
 
-	for (i = 0; i < tx_len / 4 - 1; i++)
+	for (i = 0; i < tx_len - 1; i++)
 	{
 		MST_TX_BUF[i] = i;
 	}
diff --git a/tb/sw/src/mstMainCfg.h b/tb/sw/src/mstMainCfg.h
index 1b1d7dd..841a085 100644
--- a/tb/sw/src/mstMainCfg.h
+++ b/tb/sw/src/mstMainCfg.h
@@ -1,9 +1,9 @@
 #ifndef __MSTMAINCFG_H__
 #define __MSTMAINCFG_H__
 
-#define TX_BUF_NUM          2
+#define TX_BUF_NUM          1
 #define TX_BUF_MAX_LEN      1024
-#define RX_BUF_NUM          2
+#define RX_BUF_NUM          1
 #define RX_BUF_MAX_LEN      1024
 
 #endif
diff --git a/tb/sw/src/mstSvr.S b/tb/sw/src/mstSvr.S
index 9f14f3e..5bf4152 100644
--- a/tb/sw/src/mstSvr.S
+++ b/tb/sw/src/mstSvr.S
@@ -34,6 +34,7 @@ x31, 最大的服务中断号
 #define REG_min_isr_num 	x30
 #define REG_max_isr_num		x31
 
+#define REG_4				x23
 
 .globl _prog_start
 .globl _rv32i_plic_handle
@@ -60,71 +61,21 @@ _prog_start:
 init_system_func:
 	mv		REG_plic_claim, a1 # plic_claim
 
-	/*初始化isr_hdl_table，中断表*/
-	la		x16, isr_hdl_table
-	
-	la		x17, isr_tx0_end_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_tx1_end_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx0_err_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la 		x17, isr_rx1_err_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx0_start_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx1_start_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx0_end_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx1_end_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_tx0_deq_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_tx1_deq_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx0_enq_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
-	la		x17, isr_rx1_enq_hdl
-	addi	x16, x16, 4
-	sw		x17, 0(x16)
-
 	la		x17, _rv32i_plic_handle
-
     mv		a0, x17
 
 	li		REG_TL2CDR_BASE, 	TL2CDR_BASE
 	la		REG_ISR_ADDR, 		isr_hdl_table
 	li		REG_min_isr_num, 	14
 	li		REG_max_isr_num, 	25
-	li		x23,				4
+	li		REG_4,				4
     ret
 
 //主站启动发送数据
 //a1, 当前需要发送的数据的地址
 //a2, 当前数据发送的长度
+//a3, dummy
+//a4, dummy
 send_data_func:
 	mv		REG_tx_data, 	 a1
 	mv 		REG_tx_data_len, a2
@@ -139,12 +90,11 @@ send_data_func:
 	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
 
 //*tx0_txFifo = data[0]
-	lw		x17, 0(REG_tx_data)
-	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
+	#lw		x17, 0(REG_tx_data)
+	#sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
 
-	//li		x16, 4
-	add		REG_tx_data, REG_tx_data, x23
-	sub		REG_tx_data_len, REG_tx_data_len, x23
+	#add		REG_tx_data, REG_tx_data, REG_4
+	#sub		REG_tx_data_len, REG_tx_data_len, REG_4
 	
 	li		a0,  1
 	ret
@@ -175,9 +125,13 @@ exit_handle:
 	mret
 
 isr_tx0_end_hdl:
+	#li	x17, 1
+	#sw	x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
 	mret
 
 isr_tx1_end_hdl:
+	#li	x17, 1
+	#sw	x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
 	mret
 
 isr_rx0_err_hdl:
@@ -192,7 +146,7 @@ isr_rx0_start_hdl:
 isr_rx1_start_hdl:
 	lw		x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
 	sw		x22, 0(REG_rx_data)
-	add		REG_rx_data, REG_rx_data, x23
+	add		REG_rx_data, REG_rx_data, REG_4
 	mret
 
 isr_rx0_end_hdl:
@@ -202,13 +156,12 @@ isr_rx1_end_hdl:
 	mret
 
 isr_tx0_deq_hdl:
-	bgtz	REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
+	beqz	REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
 	lw		x17, 0(REG_tx_data)
 	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
 
-	//li		x16, 4
-	add		REG_tx_data, REG_tx_data, x23
-	sub		REG_tx_data_len, REG_tx_data_len, x23
+	add		REG_tx_data, REG_tx_data, REG_4
+	sub		REG_tx_data_len, REG_tx_data_len, REG_4
 1:
 	mret
 
@@ -216,16 +169,24 @@ isr_tx1_deq_hdl:
 	mret
 
 isr_rx0_enq_hdl:
-	lw		x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
-	sw		x17, 0(REG_rx_data)
-	add		REG_rx_data, REG_rx_data, x23
 	mret
 
 isr_rx1_enq_hdl:
+	lw		x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
+	sw		x17, 0(REG_rx_data)
+	add		REG_rx_data, REG_rx_data, REG_4
 	mret
 
-	.balign 4
 isr_hdl_table:
-	.space 64
-
-	nop
\ No newline at end of file
+	j isr_tx0_end_hdl
+	j isr_tx1_end_hdl
+	j isr_rx0_err_hdl
+	j isr_rx1_err_hdl
+	j isr_rx0_start_hdl
+	j isr_rx1_start_hdl
+	j isr_rx0_end_hdl
+	j isr_rx1_end_hdl
+	j isr_tx0_deq_hdl
+	j isr_tx1_deq_hdl
+	j isr_rx0_enq_hdl
+	j isr_rx1_enq_hdl