增加新的测试用例，调整内部的延时。±176ppm测试通过，184ppm测试未通过，但差得字节数并不多，最终偏差大概在180ppm上下

tb/shinTest/ShinTopSpiTb.v

@@ -385,16 +385,16 @@ initial begin
   spi_csn  = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
 
 	//#125000
-  #250000
+  #1250000
 	reset <= 1;
 
 	//#300000
-  #600000
+  #3000000
 	reset <= 0;
 
-  #200000000000
-  #200000000000
-  #200000000000
+  #1000000000000
+  #1000000000000
+  #1000000000000
 
 	$display("Time Out !!!");
   	$fclose(spidata_file);
@@ -402,7 +402,7 @@ initial begin
 end
 
 initial begin
-	forever begin #200000 clock <= ~clock; end
+	forever begin #1000000 clock <= ~clock; end
 end
 
 
@@ -411,20 +411,32 @@ generate
     initial begin
       multiCLK[i] = 0;
       for( integer j = 0; j < i; j = j + 1 ) begin
-        #12500
+        #125000
         ;
       end
-      forever begin #200000 multiCLK[i] <= ~multiCLK[i]; end
+      forever begin #1000000 multiCLK[i] <= ~multiCLK[i]; end
     end
   end  
 endgenerate
 
-//如果频率差到 80ppm，参数是： 200016/25002/20016
-//如果频率差到120ppm，参数是： 200024/25003/20024
-//如果频率差到160ppm，参数是： 200032/25004/20032
-//如果频率差到200ppm，参数是： 200040/25005/20040
+//如果频率差到 80ppm，参数是： 1000080/125010/1000080   [pass]
+//如果频率差到120ppm，参数是： 1000120/125015/1000160   [pass]
+//如果频率差到160ppm，参数是： 1000160/125020/1000160   [pass]
+//如果频率差到168ppm，参数是： 1000168/125021/1000168   [pass]
+
+//如果频率差到176ppm，参数是： 1000176/125022/1000176   [pass]
+//如果频率差到-176ppm，参数是： 999824/124978/ 999824   [pass]
+
+//如果频率差到184ppm，参数是： 1000184/125023/1000184   [failed] //差得字节数不多，大概在180ppm上下
+//如果频率差到-184ppm，参数是： 999816/124977/ 999816
+
+//如果频率差到192ppm，参数是： 1000192/125024/1000192
+//如果频率差到-192ppm，参数是： 999808/124976/ 999808
+
+//如果频率差到200ppm，参数是： 1000200/125025/1000200
+//如果频率差到-200ppm，参数是： 999800/124975/ 999800
 initial begin
-	forever begin #200040 clock2 <= ~clock2; end
+	forever begin #1000184 clock2 <= ~clock2; end
 end
 
 generate
@@ -432,10 +444,10 @@ generate
     initial begin
       multiCLK2[i] = 0;
       for( integer j = 0; j < i; j = j + 1 ) begin
-        #25005
+        #125023
         ;
       end
-      forever begin #200040 multiCLK2[i] <= ~multiCLK2[i]; end
+      forever begin #1000184 multiCLK2[i] <= ~multiCLK2[i]; end
     end
   end  
 endgenerate
@@ -458,7 +470,7 @@ always @(negedge reset) begin
   _reset_deactive <= 1'b1;
 end
 
-  `define SCKFRE #1600000
+  `define SCKFRE #8000000
 
   reg sck = 0;
   
@@ -533,13 +545,13 @@ end
 
 always @(posedge clock) begin
   if( isReq & sck == 0 ) begin
-    isBusy   <= #12500 1'b1;
-    transCnt <= #12500 0;
+    isBusy   <= #62500 1'b1;
+    transCnt <= #62500 0;
 
-    byteCnt <= #12500 ~12'b0;
-    bitCnt  <= #12500 ~3'b0;
+    byteCnt <= #62500 ~12'b0;
+    bitCnt  <= #62500 ~3'b0;
 
-    spi_csn[idx] <= #12500 1'b0;
+    spi_csn[idx] <= #62500 1'b0;
     exChangeRego <= txBuf[0];
   end
 end
@@ -586,8 +598,8 @@ always @(posedge sck) begin
         exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
       end
     end else begin
-      isBusy       <= #12500 1'b0;
-      spi_csn[idx] <= #12500 1'b1;
+      isBusy       <= #62500 1'b0;
+      spi_csn[idx] <= #62500 1'b1;
     end
   end
 end
@@ -606,13 +618,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
     length <= slength + 3;
     idx <= sidx;
 
-    #12500
+    #62500
     @(negedge sck)
     isReq <= 1;
-    @(posedge sck) #12500
+    @(posedge sck) #62500
     isReq <= 0;
 
-    @( negedge isBusy) #2500000
+    @( negedge isBusy) #12500000
     begin 
       //$fwrite(spidata_file, "------------%5t------------\n", $realtime);
       $fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n", 
@@ -890,13 +902,13 @@ task wait_comm_finished();
         length = 8'h07;
         idx = `IF_IQSPI(0);
 
-        #12500
+        #62500
         @(negedge sck)
         isReq <= 1;
-        @(posedge sck) #12500
+        @(posedge sck) #62500
         isReq <= 0;
 
-        @( negedge isBusy) #2500000
+        @( negedge isBusy) #12500000
         begin 
             
         end
@@ -910,17 +922,17 @@ task wait_comm_finished();
             length = 8'h07;
             idx = `IF_IQSPI(0);
 
-            #12500
+            #62500
             @(negedge sck)
             isReq <= 1;
-            @(posedge sck) #12500
+            @(posedge sck) #62500
             isReq <= 0;
 
-            @( negedge isBusy) #2500000
+            @( negedge isBusy) #12500000
             begin 
                 
             end
-            #2500000
+            #12500000
             //$display("%x %x", rxBuf[3], rxBuf[6]);
             if ((rxBuf[3] & 8'h02) == 8'h02)
             begin
@@ -931,7 +943,7 @@ task wait_comm_finished();
                 $display("error occur");
                 is_run = 0;
             end
-            if (($realtime - st) >= 12500000000.0)
+            if (($realtime - st) >= 62500000000.0)
             begin
                 $display("comm timeout.");
                 is_run = 0;
@@ -943,7 +955,7 @@ endtask
 
 initial begin
 
-  #1250000
+  #6250000
 
 `ifdef ENABLE_REG_RW1_TEST
 /*---------------------------------------------------------------------------------------------------------
@@ -1096,7 +1108,7 @@ initial begin
 
   `include "tc_runlist.vh"
 
-  #2500000000
+  #12500000000
   $display("Testcase Finished! Time Out !!!");
   $fclose(spidata_file);
 	$stop;