半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的
This commit is contained in:
RuigeLee
@@ -443,9 +443,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val BlockingTxStatusWrite_sync2_txclk = Wire(Bool())
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val BlockingTxStatusWrite_sync3_txclk = Wire(Bool())
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io.RstDeferLatched := BlockingTxStatusWrite_sync2_txclk & ~BlockingTxStatusWrite_sync3_txclk
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// TxBDRead state is activated only once.
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when(StartTxBDRead){
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@@ -1110,145 +1108,166 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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class MacTileLinkTXIO extends Bundle{
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val BlockingTxStatusWrite_sync = Input(Bool())
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val TxStartFrm_sync = Input(Bool())
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val TxStartFrm = Output(Bool()) // Transmit packet start frame
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val TxEndFrm = Output(Bool()) // Transmit packet end frame
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val TxData = Output(UInt(8.W)) // Transmit packet data byte
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val TxUnderRun = Output(Bool()) // Transmit packet under-run
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val TxUsedData = Input(Bool()) // Transmit packet used data
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val TxRetry = Input(Bool()) // Transmit packet retry
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val TxAbort = Input(Bool()) // Transmit packet abort
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val TxDone = Input(Bool()) // Transmission ended
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val ReadTxDataFromFifo_tck = Output(Bool())
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val ReadTxDataFromFifo_syncb = Output(Bool())
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val TxEndFrm_wb = Input(Bool())
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val TxValidBytesLatched = Input(UInt(2.U))
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val TxData_wb = Input(UInt(32.W))
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val TxUnderRun_wb = Input(Bool())
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}
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val macTileLinkTX = Module(new MacTileLinkTX)
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macTileLinkTX.clock := io.MTxClk.asClock
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macTileLinkTX.reset := io.asyncReset
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macTileLinkTX.io.BlockingTxStatusWrite_sync := ShiftRegister(BlockingTxStatusWrite, 2, false.B, true.B)
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macTileLinkTX.io.TxStartFrm_sync := ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync// Synchronizing TxStartFrm_wb to MTxClk
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macTileLinkTX.io.ReadTxDataFromFifo_syncb := ShiftRegister(ReadTxDataFromFifo_sync(1), 2, false.B, true.B)
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io.TxStartFrm := macTileLinkTX.io.TxStartFrm
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io.TxEndFrm := macTileLinkTX.io.TxEndFrm
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io.TxData := macTileLinkTX.io.TxData
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io.TxUnderRun := macTileLinkTX.io.TxUnderRun
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macTileLinkTX.io.TxUsedData := io.TxUsedData
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macTileLinkTX.io.TxRetry := io.TxRetry
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macTileLinkTX.io.TxAbort := io.TxAbort
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macTileLinkTX.io.TxDone := io.TxDone
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class MacTileLinkTX extends Module with RequireAsyncReset{
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val io = IO(new MacTileLinkTXIO)
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io.RstDeferLatched := BlockingTxStatusWrite_sync & ~RegNext(io.BlockingTxStatusWrite_sync, false.B)
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val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun
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val TxDataLatched = RegInit(0.U(32.W))
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val TxByteCnt = RegInit(0.U(2.W))
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val LastWord = RegInit(false.B)
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val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
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// Generating delayed signals
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val TxAbort_q = RegNext( io.TxAbort, false.B)
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val TxRetry_q = RegNext( io.TxRetry, false.B)
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val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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// Changes for tx occur every second clock. Flop is used for this manner.
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val Flop = RegInit(false.B)
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when( io.TxDone | io.TxAbort | TxRetry_q){
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Flop := false.B
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} .elsewhen ( io.TxUsedData ){
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Flop := ~Flop
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}
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when(io.TxStartFrm_sync){
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TxStartFrm := true.B
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} .elsewhen(TxUsedData_q | ~io.TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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TxStartFrm := false.B
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}
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// Indication of the last word
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when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
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LastWord := false.B
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} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
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LastWord := io.TxEndFrm_wb
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}
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// Tx end frame generation
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when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
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TxEndFrm := false.B
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} .elsewhen(Flop & LastWord){
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TxEndFrm :=
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Mux1H(Seq(
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(io.TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
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(io.TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
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(io.TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
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(io.TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
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))
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}
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// Tx data selection (latching)
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when( io.TxStartFrm_sync & ~TxStartFrm ){
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TxData := io.TxData_wb( 7, 0) // little Endian Byte Ordering
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} .elsewhen(io.TxUsedData & Flop){
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TxData := Mux1H(Seq(
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(TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering
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(TxByteCnt === 1.U) -> TxDataLatched(15, 8),
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(TxByteCnt === 2.U) -> TxDataLatched(23,16),
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(TxByteCnt === 3.U) -> TxDataLatched(31,24),
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))
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}
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// Latching tx data
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when(
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io.TxStartFrm_sync & ~TxStartFrm |
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io.TxUsedData & Flop & TxByteCnt === 3.U |
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TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
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TxDataLatched := io.TxData_wb
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}
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val TxUnderRun_sync1 = RegInit(false.B)
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// Tx under run
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when(io.TxUnderRun_wb){
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TxUnderRun_sync1 := true.B
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} .elsewhen(io.BlockingTxStatusWrite_sync){
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TxUnderRun_sync1 := false.B
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}
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// Tx under run
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when(io.BlockingTxStatusWrite_sync){
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TxUnderRun := false.B
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} .elsewhen(TxUnderRun_sync1){
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TxUnderRun := true.B
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}
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// Tx Byte counter
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when(TxAbort_q | TxRetry_q){
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TxByteCnt := 0.U
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} .elsewhen(TxStartFrm & ~io.TxUsedData){
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TxByteCnt := 1.U
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} .elsewhen(io.TxUsedData & Flop){
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TxByteCnt := TxByteCnt + 1.U
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}
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when(io.TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
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~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
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ReadTxDataFromFifo_tck := true.B
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} .elsewhen(ReadTxDataFromFifo_syncb & ~RegNext(ReadTxDataFromFifo_syncb, false.B)){
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ReadTxDataFromFifo_tck := false.B
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}
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}
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trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
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val Flop = RegInit(false.B)
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// Synchronizing BlockingTxStatusWrite to MTxClk
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val BlockingTxStatusWrite_sync1 = RegNext(BlockingTxStatusWrite, false.B)
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val BlockingTxStatusWrite_sync2 = RegNext(BlockingTxStatusWrite_sync1, false.B); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2
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val BlockingTxStatusWrite_sync3 = RegNext(BlockingTxStatusWrite_sync2, false.B); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3
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// Synchronizing TxStartFrm_wb to MTxClk
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val TxStartFrm_sync = ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync
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val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun
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val TxDataLatched = RegInit(0.U(32.W))
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val TxByteCnt = RegInit(0.U(2.W))
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val LastWord = RegInit(false.B)
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val ReadTxDataFromFifo_tck = RegInit(false.B); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck
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// Generating delayed signals
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val TxAbort_q = RegNext( io.TxAbort, false.B)
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val TxRetry_q = RegNext( io.TxRetry, false.B)
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val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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val ReadTxDataFromFifo_syncb = ShiftRegisters(ReadTxDataFromFifo_sync(1), 3, false.B, true.B)
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// Changes for tx occur every second clock. Flop is used for this manner.
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when( io.TxDone | io.TxAbort | TxRetry_q){
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Flop := false.B
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} .elsewhen ( io.TxUsedData ){
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Flop := ~Flop
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}
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when(TxStartFrm_sync){
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TxStartFrm := true.B
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} .elsewhen(TxUsedData_q | ~TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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TxStartFrm := false.B
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}
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// Indication of the last word
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when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
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LastWord := false.B
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} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
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LastWord := TxEndFrm_wb
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}
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// Tx end frame generation
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when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
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TxEndFrm := false.B
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} .elsewhen(Flop & LastWord){
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TxEndFrm :=
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Mux1H(Seq(
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(TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
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(TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
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(TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
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(TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
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))
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}
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// Tx data selection (latching)
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when( TxStartFrm_sync & ~TxStartFrm ){
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TxData := TxData_wb( 7, 0) // little Endian Byte Ordering
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} .elsewhen(io.TxUsedData & Flop){
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TxData := Mux1H(Seq(
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(TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering
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(TxByteCnt === 1.U) -> TxDataLatched(15, 8),
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(TxByteCnt === 2.U) -> TxDataLatched(23,16),
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(TxByteCnt === 3.U) -> TxDataLatched(31,24),
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))
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}
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// Latching tx data
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when(
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TxStartFrm_sync & ~TxStartFrm |
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io.TxUsedData & Flop & TxByteCnt === 3.U |
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TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
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TxDataLatched := TxData_wb
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}
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val TxUnderRun_sync1 = RegInit(false.B)
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// Tx under run
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when(TxUnderRun_wb){
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TxUnderRun_sync1 := true.B
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} .elsewhen(BlockingTxStatusWrite_sync2){
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TxUnderRun_sync1 := false.B
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}
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// Tx under run
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when(BlockingTxStatusWrite_sync2){
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TxUnderRun := false.B
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} .elsewhen(TxUnderRun_sync1){
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TxUnderRun := true.B
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}
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// Tx Byte counter
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when(TxAbort_q | TxRetry_q){
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TxByteCnt := 0.U
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} .elsewhen(TxStartFrm & ~io.TxUsedData){
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TxByteCnt := 1.U
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} .elsewhen(io.TxUsedData & Flop){
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TxByteCnt := TxByteCnt + 1.U
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}
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when(TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
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~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
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ReadTxDataFromFifo_tck := true.B
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} .elsewhen(ReadTxDataFromFifo_syncb(1) & ~ReadTxDataFromFifo_syncb(2)){
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ReadTxDataFromFifo_tck := false.B
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}
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}
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}
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@@ -1256,6 +1275,137 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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// trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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// withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
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// val Flop = RegInit(false.B)
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// val BlockingTxStatusWrite_sync = ShiftRegisters(BlockingTxStatusWrite, 3, false.B, true.B) // Synchronizing BlockingTxStatusWrite to MTxClk
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// io.RstDeferLatched := BlockingTxStatusWrite_sync(1) & ~BlockingTxStatusWrite_sync(2)
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// val TxStartFrm_sync = ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync// Synchronizing TxStartFrm_wb to MTxClk
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// val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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// val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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// val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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// val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun
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// val TxDataLatched = RegInit(0.U(32.W))
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// val TxByteCnt = RegInit(0.U(2.W))
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// val LastWord = RegInit(false.B)
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// val ReadTxDataFromFifo_tck = RegInit(false.B); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck
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// // Generating delayed signals
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// val TxAbort_q = RegNext( io.TxAbort, false.B)
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// val TxRetry_q = RegNext( io.TxRetry, false.B)
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// val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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// val ReadTxDataFromFifo_syncb = ShiftRegisters(ReadTxDataFromFifo_sync(1), 3, false.B, true.B)
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// // Changes for tx occur every second clock. Flop is used for this manner.
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// when( io.TxDone | io.TxAbort | TxRetry_q){
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// Flop := false.B
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// } .elsewhen ( io.TxUsedData ){
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// Flop := ~Flop
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// }
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// when(TxStartFrm_sync){
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// TxStartFrm := true.B
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// } .elsewhen(TxUsedData_q | ~TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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// TxStartFrm := false.B
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// }
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// // Indication of the last word
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// when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
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// LastWord := false.B
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// } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
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// LastWord := TxEndFrm_wb
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// }
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// // Tx end frame generation
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// when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
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// TxEndFrm := false.B
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// } .elsewhen(Flop & LastWord){
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// TxEndFrm :=
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// Mux1H(Seq(
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// (TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
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// (TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
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// (TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
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// (TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
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// ))
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// }
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// // Tx data selection (latching)
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// when( TxStartFrm_sync & ~TxStartFrm ){
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// TxData := TxData_wb( 7, 0) // little Endian Byte Ordering
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// } .elsewhen(io.TxUsedData & Flop){
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// TxData := Mux1H(Seq(
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// (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering
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// (TxByteCnt === 1.U) -> TxDataLatched(15, 8),
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// (TxByteCnt === 2.U) -> TxDataLatched(23,16),
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// (TxByteCnt === 3.U) -> TxDataLatched(31,24),
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// ))
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// }
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// // Latching tx data
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// when(
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// TxStartFrm_sync & ~TxStartFrm |
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// io.TxUsedData & Flop & TxByteCnt === 3.U |
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// TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
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// TxDataLatched := TxData_wb
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// }
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// val TxUnderRun_sync1 = RegInit(false.B)
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// // Tx under run
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// when(TxUnderRun_wb){
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// TxUnderRun_sync1 := true.B
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// } .elsewhen(BlockingTxStatusWrite_sync(1)){
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// TxUnderRun_sync1 := false.B
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// }
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// // Tx under run
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// when(BlockingTxStatusWrite_sync(1)){
|
||||
// TxUnderRun := false.B
|
||||
// } .elsewhen(TxUnderRun_sync1){
|
||||
// TxUnderRun := true.B
|
||||
// }
|
||||
|
||||
|
||||
|
||||
// // Tx Byte counter
|
||||
// when(TxAbort_q | TxRetry_q){
|
||||
// TxByteCnt := 0.U
|
||||
// } .elsewhen(TxStartFrm & ~io.TxUsedData){
|
||||
// TxByteCnt := 1.U
|
||||
// } .elsewhen(io.TxUsedData & Flop){
|
||||
// TxByteCnt := TxByteCnt + 1.U
|
||||
// }
|
||||
|
||||
// when(TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
|
||||
// ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
|
||||
// ReadTxDataFromFifo_tck := true.B
|
||||
// } .elsewhen(ReadTxDataFromFifo_syncb(1) & ~ReadTxDataFromFifo_syncb(2)){
|
||||
// ReadTxDataFromFifo_tck := false.B
|
||||
// }
|
||||
|
||||
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user