暂时改回4倍采样以实现FPGA逻辑

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -13,7 +13,7 @@ class CDRInIO extends Bundle{
 
 
 abstract class CDRInBase extends Module{
-  def sampleRate: Int = 8
+  def sampleRate: Int = 4
 
   val io: CDRInIO = IO(new CDRInIO)
 

tb/shinTest/ShinTopSpiTb.v

@@ -146,7 +146,7 @@ initial begin
 end
 
 initial begin
-	forever begin #10 clk8x <= ~clk8x; end
+	forever begin #20 clk8x <= ~clk8x; end
 end
 
 initial begin