暂时改回4倍采样以实现FPGA逻辑

2025-05-13 17:05:38 +08:00
parent a39a15e1d0
commit fb8bc91947
2 changed files with 2 additions and 2 deletions
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -13,7 +13,7 @@ class CDRInIO extends Bundle{


 abstract class CDRInBase extends Module{
-  def sampleRate: Int = 8
+  def sampleRate: Int = 4

  val io: CDRInIO = IO(new CDRInIO)