diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 7c73053..824f2fd 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -39,7 +39,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   //数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
   val shiftSCK  = ShiftRegisters(sck, 3, false.B, true.B)
   val shiftCSn  = ShiftRegisters(csn, 3, true.B, true.B)
-  val shiftMOSI = Wire(Bool())
+
 
 
   val isSckPosedge     = ~shiftSCK(2) &  shiftSCK(1)
@@ -87,6 +87,56 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
     spiCnt := spiCnt + 1.U
   }
 
+  val shiftMOSI = Wire(Bool())
+}
+
+trait SpiOp444 extends SpiInterfaceBase{
+  val shiftDat = Wire(UInt(4.W))
+
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    spiLenTemp := 0.U
+    spiLen     := 2.U
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 2.U){ //CS为低，且SCK上跳的第0byte
+    spiLenTemp := Cat( shiftDat, 0.U(8.W) )
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 3.U) {//CS为低，且SCK上跳的第0byte
+    spiLenTemp := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
+    spiLen     := Cat(spiLenTemp(11,8), exRegi(3,0), shiftDat)
+  }
+
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    addrr := 0.U
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
+    addrr := Cat( exRegi(3,0), shiftDat)
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
+    addrr := Cat(addrr(7,0), exRegi(3,0), shiftDat)
+  } .otherwise{ // byteSel > 1.U
+    when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){
+      addrr := addrr + 1.U
+    }
+  }
+
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    addrw := 0.U
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
+    addrw := Cat( exRegi(3,0), shiftDat )
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
+    addrw := Cat(addrw(7,0), exRegi(3,0), shiftDat )
+  } .otherwise{ // byteSel > 1.U
+    when( isSckPosedgeNext(0) & byteSelNext >= 4.U & bitSelNext.andR ){
+      addrw := addrw + 1.U
+    }
+  }
+
+  when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){  //CS下跳或上跳
+    spiCmd := 0.U
+  } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
+    spiCmd := shiftDat.extract(3)
+  }
+}
+
+trait SpiOp114 extends SpiInterfaceBase{
+
+
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     spiLenTemp := 0.U
     spiLen     := 2.U
@@ -128,7 +178,8 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   }
 }
 
-class SSpiInterface extends SpiInterfaceBase{
+
+class SSpi extends SpiInterfaceBase with SpiOp114{
   val spi = IO(new SSPIInterfaceIO)
   shiftMOSI := ShiftRegister(spi.mosi, 2, false.B, true.B)
 
@@ -168,49 +219,19 @@ class SSpiInterface extends SpiInterfaceBase{
 
 }
 
-class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
+
+
+
+trait QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
   val qspi = IO(new QSPIInterfaceIO)
-  val shiftDat = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
-  shiftMOSI := shiftDat(1).extract(0)
+  shiftDat := ShiftRegister(qspi.mosi, 2, 0.U(4.W), true.B)
+  shiftMOSI := shiftDat.extract(0)
 
   sck       := qspi.sck
   csn       := qspi.csn
   qspi.miso := exRego(7, 4)
   qspi.isDirIn := isSpiWrite || byteSel < 4.U
 
-
-
-
-
-
-  when( shiftCSn(2) & ~shiftCSn(1) ){
-    bitSel := 0.U
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
-    when( byteSel <= 3.U ){
-      bitSel := bitSel + 1.U      
-    } .otherwise{
-      bitSel := ~bitSel
-    }
-  }
-
-
-  //输入看SCK上升沿
-  when( isSckPosedge & ~shiftCSn(1) ){
-    when( byteSel <= 3.U ){
-      when( bitSel === 0.U ){
-        exRegi := Cat( 0.U, shiftMOSI )
-      }.otherwise{
-        exRegi := Cat( exRegi(6,0), shiftMOSI )
-      }
-    } .otherwise{
-      when( bitSel === 0.U ){
-        exRegi := Cat( 0.U, shiftDat(1) )
-      }.otherwise{
-        exRegi := Cat( exRegi(3,0), shiftDat(1) )
-      }
-    }
-  }
-
   //输出在SCK XX沿准备数据
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     exRego := 0.U //第一个byte 地址0
@@ -229,8 +250,55 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
     }
   }
 
+}
 
 
+class QSpi444 extends SpiInterfaceBase with SpiOp444 with QSpiInterface{
+  //输入看SCK上升沿
+  when( isSckPosedge & ~shiftCSn(1) ){
+    when( bitSel === 0.U ){
+      exRegi := Cat( 0.U, shiftDat )
+    }.otherwise{
+      exRegi := Cat( exRegi(3,0), shiftDat )
+    }
+  }
+
+  when( shiftCSn(2) & ~shiftCSn(1) ){
+    bitSel := 0.U
+  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
+    bitSel := ~bitSel
+  }
+
+}
+
+class QSpi114 extends SpiInterfaceBase with SpiOp114 with QSpiInterface{
+  //输入看SCK上升沿
+  when( isSckPosedge & ~shiftCSn(1) ){
+    when( byteSel <= 3.U ){
+      when( bitSel === 0.U ){
+        exRegi := Cat( 0.U, shiftMOSI )
+      }.otherwise{
+        exRegi := Cat( exRegi(6,0), shiftMOSI )
+      }
+    } .otherwise{
+      when( bitSel === 0.U ){
+        exRegi := Cat( 0.U, shiftDat )
+      }.otherwise{
+        exRegi := Cat( exRegi(3,0), shiftDat )
+      }
+    }
+  }
+
+  when( shiftCSn(2) & ~shiftCSn(1) ){
+    bitSel := 0.U
+  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
+    when( byteSel <= 3.U ){
+      bitSel := bitSel + 1.U      
+    } .otherwise{
+      bitSel := ~bitSel
+    }
+  }
+
 }