From fb26a40061b2ca3a52da294d9adc65142e5a2f42 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 18 Sep 2025 15:23:57 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E5=90=8C=E6=AD=A5QSPI?= =?UTF-8?q?=E4=BD=BF=E7=94=A8csn=E5=BC=82=E6=AD=A5=E5=A4=8D=E4=BD=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/NSpiInterface.scala | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala index 6438427..4018b14 100644 --- a/src/main/scala/backBoard/shin/NSpiInterface.scala +++ b/src/main/scala/backBoard/shin/NSpiInterface.scala @@ -9,21 +9,21 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{ val io = IO(new RegAccessInterfaceIO) val qspi = IO(new QSPIInterfaceIO) - val bitSel = withClockAndReset((~qspi.sck).asClock, qspi.csn){RegInit(0.U(3.W)) } - val byteSel = withClockAndReset((~qspi.sck).asClock, qspi.csn){RegInit(0.U(12.W))} - val exRego = withClockAndReset((~qspi.sck).asClock, qspi.csn){RegInit(0.U(8.W))} - val exRegi = withClockAndReset((~qspi.sck).asClock, qspi.csn){RegInit(0.U(8.W))} - val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(0.U(16.W)) } } - val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(0.U(16.W)) } } - val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(0.U(8.W)) } } - val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(false.B) } } - val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(false.B) } } + val bitSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) } + val byteSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(12.W))} + val exRego = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} + val exRegi = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} + val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } + val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } + val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } } + val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } } + val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } } - val spiLen = withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(2.U(12.W)) } - val spiCnt = withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(0.U(12.W)) } - val isSpiWrite = withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(false.B) } - val isSpiRead = withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(false.B) } - val isPing_async = withClockAndReset((~qspi.sck).asClock, qspi.csn){ RegInit(false.B) } + val spiLen = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } + val spiCnt = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) } + val isSpiWrite = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } + val isSpiRead = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } + val isPing_async = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }