From faf8abc29a9211b6bc75c6f3578c10a41c64d943 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 22 Jan 2025 17:12:40 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8A=A0=E5=85=A5=E5=A4=96=E8=AE=BE=E5=A4=B4?= =?UTF-8?q?=E6=96=87=E4=BB=B6=EF=BC=8C=E7=A7=BB=E5=8A=A8=E4=B8=AD=E6=96=AD?= =?UTF-8?q?=E7=BC=96=E5=8F=B7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/sw/axi_gpio/gpio.c | 40 ------- tb/sw/axi_gpio/gpio.h | 24 ----- tb/sw/axi_timer/timer.c | 232 ---------------------------------------- tb/sw/axi_timer/timer.h | 50 --------- tb/sw/axi_uart/uart.c | 78 -------------- tb/sw/axi_uart/uart.h | 26 ----- tb/sw/periph/gpio.h | 36 +++++++ tb/sw/periph/i2c.h | 13 +++ tb/sw/periph/pwm.h | 21 ++++ tb/sw/periph/spi.h | 31 ++++++ tb/sw/periph/uart.h | 31 ++++++ tb/sw/src/MstMain.c | 32 +++--- tb/sw/src/SlvMain.c | 22 ++-- tb/verilator/SimTop.v | 130 +++++++++++++++++++++- 14 files changed, 292 insertions(+), 474 deletions(-) delete mode 100644 tb/sw/axi_gpio/gpio.c delete mode 100644 tb/sw/axi_gpio/gpio.h delete mode 100644 tb/sw/axi_timer/timer.c delete mode 100644 tb/sw/axi_timer/timer.h delete mode 100644 tb/sw/axi_uart/uart.c delete mode 100644 tb/sw/axi_uart/uart.h create mode 100644 tb/sw/periph/gpio.h create mode 100644 tb/sw/periph/i2c.h create mode 100644 tb/sw/periph/pwm.h create mode 100644 tb/sw/periph/spi.h create mode 100644 tb/sw/periph/uart.h diff --git a/tb/sw/axi_gpio/gpio.c b/tb/sw/axi_gpio/gpio.c deleted file mode 100644 index 30c4290..0000000 --- a/tb/sw/axi_gpio/gpio.c +++ /dev/null @@ -1,40 +0,0 @@ - -#include -#include "gpio.h" - - - - -#ifndef GPIO_BASE -#error GPIO Base address not define!!! -#endif - - -// for 8 bit gpio - -volatile uint32_t *gpio_dat_reg = (uint32_t*)( GPIO_BASE + GPIO_DATA ); -volatile uint32_t *gpio_tri_reg = (uint32_t*)( GPIO_BASE + GPIO_TRI ); - - -uint8_t gpio_read() -{ - *gpio_tri_reg = 0xff; - return (uint8_t)(*gpio_dat_reg); -} - - -uint32_t gpio_write( uint32_t data ) -{ - *gpio_tri_reg = 0x00; - (*gpio_dat_reg) = data; - return 0; -} - - - - - - - - - diff --git a/tb/sw/axi_gpio/gpio.h b/tb/sw/axi_gpio/gpio.h deleted file mode 100644 index 91cbcbc..0000000 --- a/tb/sw/axi_gpio/gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#include - -#define GPIO_BASE 0x20000000U - - - -#define GPIO_DATA 0x0000 -#define GPIO_TRI 0x0004 -#define GPIO2_DATA 0x0008 -#define GPIO2_TRI 0x000C -#define GIER 0x011C -#define IP_IER 0x0128 -#define IP_ISR 0x0120 - - -extern uint8_t gpio_read(); -extern uint32_t gpio_write( uint32_t data ); - -void gpio_test(); - -#endif diff --git a/tb/sw/axi_timer/timer.c b/tb/sw/axi_timer/timer.c deleted file mode 100644 index a94a1e4..0000000 --- a/tb/sw/axi_timer/timer.c +++ /dev/null @@ -1,232 +0,0 @@ -/* -* @Author: Ruige Lee -* @Date: 2020-10-12 14:27:54 -* @Last Modified by: Ruige Lee -* @Last Modified time: 2020-10-12 17:16:04 -*/ - - -#include -#include "timer.h" - - -#ifndef TIMER_BASE -#error Timer Base address not define!!! -#endif - - - - -volatile uint32_t *timer_tcsr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR0 ); -volatile uint32_t *timer_tlr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR0 ); -volatile uint32_t *timer_tcr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR0 ); - - -volatile uint32_t *timer_tcsr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR1 ); -volatile uint32_t *timer_tlr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR1 ); -volatile uint32_t *timer_tcr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR1 ); - - -int32_t timerIsINT(uint8_t timerNo) -{ - if ( ( ( (*timer_tcsr0_reg) & 0x00000100 ) && ( timerNo == 0 ) ) - || - ( ( (*timer_tcsr1_reg) & 0x00000100 ) && ( timerNo == 1 ) ) - ) - { - return 1; - } - else - { - return 0; - } -} - -int32_t timerClearINT(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000100; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000100; - } - - return 0; -} - -int32_t timerEnableRun(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000080; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000080; - } - - return 0; -} - -int32_t timerDisableRun(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000080); - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000080); - } - - return 0; -} - -int32_t timerEnableINT(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000020); - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000040; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000020); - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000040; - } - - - return 0; -} - -int32_t timerDisableINT(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000040); - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000040); - } - return 0; -} - -int32_t timerLoad(uint8_t timerNo, uint32_t count) -{ - if ( timerNo == 0 ) - { - *timer_tlr0_reg = count; - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000020; - } - else - { - *timer_tlr1_reg = count; - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000020; - } - - return 0; -} - - -int32_t timerAutoReloadEnable(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000010; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000010; - } - - return 0; -} - -int32_t timerAutoReloadDisable(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000010); - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000010); - } - - - return 0; -} - -int32_t timerUpCount(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000002); - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000002); - } - - - return 0; -} - -int32_t timerDownCount(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000002; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000002; - } - - return 0; -} - -int32_t timerGenerate(uint8_t timerNo) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000001); - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000001); - } - - return 0; -} - -int32_t timerCapture( uint8_t timerNo ) -{ - if ( timerNo == 0 ) - { - *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000001; - } - else - { - *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000001; - } - - return 0; -} - -uint32_t timerCounterRead( uint8_t timerNo ) -{ - if ( timerNo == 0 ) - { - return *timer_tcr0_reg; - } - else - { - return *timer_tcr1_reg; - } -} - - diff --git a/tb/sw/axi_timer/timer.h b/tb/sw/axi_timer/timer.h deleted file mode 100644 index 5ec502f..0000000 --- a/tb/sw/axi_timer/timer.h +++ /dev/null @@ -1,50 +0,0 @@ - - -#ifndef _TIMER_H_ -#define _TIMER_H_ - - -#include - - - -#define TIMER_BASE 0x20000800U - - -#define TIMER_TCSR0 0x00U -#define TIMER_TLR0 0x04 -#define TIMER_TCR0 0x08 - -// #define TIMER_RSVD - -#define TIMER_TCSR1 0x10U -#define TIMER_TLR1 0x14U -#define TIMER_TCR1 0x18U - - -extern int32_t timerIsINT( uint8_t timerNo ); -extern int32_t timerClearINT( uint8_t timerNo ); -extern int32_t timerEnableRun( uint8_t timerNo ); -extern int32_t timerDisableRun( uint8_t timerNo ); -extern int32_t timerEnableINT( uint8_t timerNo ); -extern int32_t timerDisableINT( uint8_t timerNo ); -extern int32_t timerLoad( uint8_t timerNo, uint32_t count ); -extern int32_t timerAutoReloadEnable( uint8_t timerNo ); -extern int32_t timerAutoReloadDisable( uint8_t timerNo ); -extern int32_t timerUpCount( uint8_t timerNo ); -extern int32_t timerDownCount( uint8_t timerNo ); -extern int32_t timerGenerate( uint8_t timerNo ); -extern int32_t timerCapture( uint8_t timerNo ); -extern uint32_t timerCounterRead( uint8_t timerNo ); - - - - - - - - -#endif - - - diff --git a/tb/sw/axi_uart/uart.c b/tb/sw/axi_uart/uart.c deleted file mode 100644 index c52389a..0000000 --- a/tb/sw/axi_uart/uart.c +++ /dev/null @@ -1,78 +0,0 @@ - - -#include -#include "uart.h" - - -#ifndef UART_BASE -#error UART Base address not define!!! -#endif - - -volatile uint32_t *uart_rfifo = (uint32_t*)( UART_BASE + RX_FIFO ); -volatile uint32_t *uart_tfifo = (uint32_t*)( UART_BASE + TX_FIFO ); -volatile uint32_t *uart_status = (uint32_t*)( UART_BASE + STAT_REG ); -volatile uint32_t *uart_ctrl = (uint32_t*)( UART_BASE + CTRL_REG ); - - -int32_t uart_init() -{ - //reset rx & tx fifo, disable interrupt - (*uart_status) = 0x03; - (*uart_status) = 0x00; - - return 0; -} - - - -int32_t uart_sendByte( uint8_t data ) -{ - #if(1) - //wait unitl tx fifo not full - while( ((*uart_status) & 0x08) != 0); - *uart_tfifo = data; - #else - (*(volatile uint32_t*)(0x60000000)) = data; - #endif - - return 0; -} - - -uint8_t uart_recByte() -{ - //wait unitl rx fifo has data - while( ((*uart_status) & 0x01) == 0); - - return (uint8_t)(*uart_rfifo); -} - - - -int32_t print_uart(const char *str) -{ - const char *cur = &str[0]; - while (*cur != '\0') - { - uart_sendByte((uint8_t)*cur); - cur++; - } - - return 0; -} - - - - - - - - - - - - - - - diff --git a/tb/sw/axi_uart/uart.h b/tb/sw/axi_uart/uart.h deleted file mode 100644 index e86db02..0000000 --- a/tb/sw/axi_uart/uart.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _UART_H_ -#define _UART_H_ - -#include - -#define UART_BASE 0x60000000U - - - -#define RX_FIFO 0x0000 -#define TX_FIFO 0x0004 -#define STAT_REG 0x0008 -#define CTRL_REG 0x000c - - -extern int32_t uart_init(); -extern int32_t uart_sendByte( uint8_t data ); -extern uint8_t uart_recByte(); -extern int32_t print_uart(const char *str); - - - - -#endif - - diff --git a/tb/sw/periph/gpio.h b/tb/sw/periph/gpio.h new file mode 100644 index 0000000..a97d0e8 --- /dev/null +++ b/tb/sw/periph/gpio.h @@ -0,0 +1,36 @@ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + +#define GPIO_BASE 0x3000000U + +#define GPIO_VALUE 0x00 +#define GPIO_INPUT_EN 0x04 +#define GPIO_OUTPUT_EN 0x08 +#define GPIO_PORT 0x0c +#define GPIO_PULLUP_EN 0x10 +#define GPIO_DRIVE 0x14 +#define GPIO_RISE_IE 0x18 +#define GPIO_RISE_IP 0x1c +#define GPIO_FALL_IE 0x20 +#define GPIO_FALL_IP 0x24 +#define GPIO_HIGH_IE 0x28 +#define GPIO_HIGH_IP 0x2c +#define GPIO_LOW_IE 0x30 +#define GPIO_LOW_IP 0x34 +#define GPIO_IOF_EN 0x38 +#define GPIO_IOF_SEL 0x3c +#define GPIO_OUT_XOR 0x40 +#define GPIO_PASSTHRU_HIGH_IE 0x44 +#define GPIO_PASSTHRU_LOW_IE 0x48 +#define GPIO_PS 0x4c +#define GPIO_POE 0x50 + + + + + + + +#endif diff --git a/tb/sw/periph/i2c.h b/tb/sw/periph/i2c.h new file mode 100644 index 0000000..b2ef117 --- /dev/null +++ b/tb/sw/periph/i2c.h @@ -0,0 +1,13 @@ +#ifndef _I2C_H_ +#define _I2C_H_ + +#include + +#define I2C_BASE 0x3040000U + +#define I2C_PRESCALER_LO 0x00 // low byte clock prescaler register +#define I2C_PRESCALER_HI 0x04 // high byte clock prescaler register +#define I2C_CONTROL 0x08 // control register +#define I2C_DATA 0x0c // write: transmit byte, read: receive byte +#define I2C_CMD_STATUS 0x10 // write: command, read: status + diff --git a/tb/sw/periph/pwm.h b/tb/sw/periph/pwm.h new file mode 100644 index 0000000..34975d0 --- /dev/null +++ b/tb/sw/periph/pwm.h @@ -0,0 +1,21 @@ +#ifndef _PWM_H_ +#define _PWM_H_ + +#include + +#define PWM_BASE 0x3020000U + +#define CFG 0x00 + +#define COUNT 0x08 + +#define PWMS 0x10 + +#define CMP0 0x20 +#define CMP1 0x24 +#define CMP2 0x28 +#define CMP3 0x2C + + + + diff --git a/tb/sw/periph/spi.h b/tb/sw/periph/spi.h new file mode 100644 index 0000000..9e9a011 --- /dev/null +++ b/tb/sw/periph/spi.h @@ -0,0 +1,31 @@ +#ifndef _SPI_H_ +#define _SPI_H_ + +#include + +#define SPI_BASE 0x3030000U + +#define SPI_SCKDIV 0x00 +#define SPI_SCKMODE 0x04 +#define SPI_CSID 0x10 +#define SPI_CSDEF 0x14 +#define SPI_CSMODE 0x18 +#define SPI_DCSSCK 0x28 +#define SPI_DSCKCS 0x2a +#define SPI_DINTERCS 0x2c +#define SPI_DINTERXFR 0x2e +#define SPI_EXTRADEL 0x38 +#define SPI_SAMPLEDEL 0x3c +#define SPI_FMT 0x40 +#define SPI_LEN 0x42 +#define SPI_TXFIFO 0x48 +#define SPI_RXFIFO 0x4c +#define SPI_TXMARK 0x50 +#define SPI_RXMARK 0x54 +#define SPI_INSNMODE 0x60 +#define SPI_INSNFMT 0x64 +#define SPI_INSNPROTO 0x65 +#define SPI_INSNCMD 0x66 +#define SPI_INSNPAD 0x67 +#define SPI_IE 0x70 +#define SPI_IP 0x74 \ No newline at end of file diff --git a/tb/sw/periph/uart.h b/tb/sw/periph/uart.h new file mode 100644 index 0000000..df650ef --- /dev/null +++ b/tb/sw/periph/uart.h @@ -0,0 +1,31 @@ +#ifndef _UART_H_ +#define _UART_H_ + +#include + +#define UART_BASE 0x3010000U + + + +#define UART_TXFIFO 0x00 +#define UART_RXFIFO 0x04 +#define UART_TXCTRL 0x08 +#define UART_TXMARK 0x0a +#define UART_RXCTRL 0x0c +#define UART_RXMARK 0x0e +#define UART_IE 0x10 +#define UART_IP 0x14 +#define UART_DIV 0x18 +#define UART_PARITY 0x1c +#define UART_WIRE4 0x20 +#define UART_EITHER8OR9 0x24 + + + + + + + +#endif + + diff --git a/tb/sw/src/MstMain.c b/tb/sw/src/MstMain.c index 1fd5d34..199a25e 100644 --- a/tb/sw/src/MstMain.c +++ b/tb/sw/src/MstMain.c @@ -10,6 +10,10 @@ volatile uint32_t *plic_priority_4 = (uint32_t*)( 0xc000000U + 0X000004 * 4); volatile uint32_t *plic_priority_5 = (uint32_t*)( 0xc000000U + 0X000004 * 5); volatile uint32_t *plic_priority_6 = (uint32_t*)( 0xc000000U + 0X000004 * 6); +volatile uint32_t *plic_priority_18 = (uint32_t*)( 0xc000000U + 0X000004 * 18); +volatile uint32_t *plic_priority_19 = (uint32_t*)( 0xc000000U + 0X000004 * 19); +volatile uint32_t *plic_priority_20 = (uint32_t*)( 0xc000000U + 0X000004 * 20); +volatile uint32_t *plic_priority_21 = (uint32_t*)( 0xc000000U + 0X000004 * 21); volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 ); volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 ); @@ -31,13 +35,13 @@ void plic_handle(){ uint32_t claim = *plic_claim; - if( claim == 3 ){ + if( claim == 18 ){ flag_intTxEnd = 1; - } else if( claim == 4 ){ + } else if( claim == 19 ){ flag_intRxError = 1; - } else if( claim == 5 ){ + } else if( claim == 20 ){ flag_intRxStart = 1; - } else if( claim == 6 ){ + } else if( claim == 21 ){ flag_intRxEnd = 1; } @@ -78,19 +82,19 @@ void main() uint32_t led = 0; - *plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6; - *plic_priority_3 = 1; - *plic_priority_4 = 1; - *plic_priority_5 = 1; - *plic_priority_6 = 1; + *plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21; + *plic_priority_18 = 1; + *plic_priority_19 = 1; + *plic_priority_20 = 1; + *plic_priority_21 = 1; *plic_threshold_0 = 0; {//再写一次实现延迟，等从机的复位完成 - *plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6; - *plic_priority_3 = 1; - *plic_priority_4 = 1; - *plic_priority_5 = 1; - *plic_priority_6 = 1; + *plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21; + *plic_priority_18 = 1; + *plic_priority_19 = 1; + *plic_priority_20 = 1; + *plic_priority_21 = 1; *plic_threshold_0 = 0; } diff --git a/tb/sw/src/SlvMain.c b/tb/sw/src/SlvMain.c index f97d3cc..ed0b3ca 100644 --- a/tb/sw/src/SlvMain.c +++ b/tb/sw/src/SlvMain.c @@ -10,6 +10,10 @@ volatile uint32_t *plic_priority_4 = (uint32_t*)( 0xc000000U + 0X000004 * 4); volatile uint32_t *plic_priority_5 = (uint32_t*)( 0xc000000U + 0X000004 * 5); volatile uint32_t *plic_priority_6 = (uint32_t*)( 0xc000000U + 0X000004 * 6); +volatile uint32_t *plic_priority_18 = (uint32_t*)( 0xc000000U + 0X000004 * 18); +volatile uint32_t *plic_priority_19 = (uint32_t*)( 0xc000000U + 0X000004 * 19); +volatile uint32_t *plic_priority_20 = (uint32_t*)( 0xc000000U + 0X000004 * 20); +volatile uint32_t *plic_priority_21 = (uint32_t*)( 0xc000000U + 0X000004 * 21); volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 ); volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 ); @@ -31,13 +35,13 @@ void plic_handle(){ uint32_t claim = *plic_claim; - if( claim == 3 ){ + if( claim == 18 ){ flag_intTxEnd = 1; - } else if( claim == 4 ){ + } else if( claim == 19 ){ flag_intRxError = 1; - } else if( claim == 5 ){ + } else if( claim == 20 ){ flag_intRxStart = 1; - } else if( claim == 6 ){ + } else if( claim == 21 ){ flag_intRxEnd = 1; } @@ -75,11 +79,11 @@ void main() register uint32_t isLast; register uint32_t flag; - *plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6; - *plic_priority_3 = 1; - *plic_priority_4 = 1; - *plic_priority_5 = 1; - *plic_priority_6 = 1; + *plic_enable_0_31 = 1 << 18 | 1 << 19 | 1 << 20 | 1 << 21; + *plic_priority_18 = 1; + *plic_priority_19 = 1; + *plic_priority_20 = 1; + *plic_priority_21 = 1; *plic_threshold_0 = 0; diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v index 7207afa..08a1501 100644 --- a/tb/verilator/SimTop.v +++ b/tb/verilator/SimTop.v @@ -13,7 +13,10 @@ module SimTop ( input clock, //100MHz input reset, - input clk400 + input clk400, + + output [7:0] gpio_o, + input [7:0] gpio_i ); @@ -75,6 +78,131 @@ ExampleRocketSystem s_rocket_mst( .mmio_ahb_0_hmaster(), .mmio_ahb_0_hsplit(16'b0), + .gpio_0_pins_0_i_ival(gpio_i[0]), //输入 + .gpio_0_pins_0_i_po(1'b0), // + .gpio_0_pins_0_o_oval(gpio_o[0]), //输出 + .gpio_0_pins_0_o_oe(), //输出使能 + .gpio_0_pins_0_o_ie(), //输入使能 + .gpio_0_pins_0_o_pue(), //上拉使能 + .gpio_0_pins_0_o_ds(), //驱动强度 + .gpio_0_pins_0_o_ps(), //驱动速率？ + .gpio_0_pins_0_o_ds1(), //驱动强度？ + .gpio_0_pins_0_o_poe(), //Nandtree enable + + .gpio_0_pins_1_i_ival(gpio_i[1]), + .gpio_0_pins_1_i_po(1'b0), + .gpio_0_pins_1_o_oval(gpio_o[1]), + .gpio_0_pins_1_o_oe(), + .gpio_0_pins_1_o_ie(), + .gpio_0_pins_1_o_pue(), + .gpio_0_pins_1_o_ds(), + .gpio_0_pins_1_o_ps(), + .gpio_0_pins_1_o_ds1(), + .gpio_0_pins_1_o_poe(), + + .gpio_0_pins_2_i_ival(gpio_i[2]), + .gpio_0_pins_2_i_po(1'b0), + .gpio_0_pins_2_o_oval(gpio_o[2]), + .gpio_0_pins_2_o_oe(), + .gpio_0_pins_2_o_ie(), + .gpio_0_pins_2_o_pue(), + .gpio_0_pins_2_o_ds(), + .gpio_0_pins_2_o_ps(), + .gpio_0_pins_2_o_ds1(), + .gpio_0_pins_2_o_poe(), + + .gpio_0_pins_3_i_ival(gpio_i[3]), + .gpio_0_pins_3_i_po(1'b0), + .gpio_0_pins_3_o_oval(gpio_o[3]), + .gpio_0_pins_3_o_oe(), + .gpio_0_pins_3_o_ie(), + .gpio_0_pins_3_o_pue(), + .gpio_0_pins_3_o_ds(), + .gpio_0_pins_3_o_ps(), + .gpio_0_pins_3_o_ds1(), + .gpio_0_pins_3_o_poe(), + + .gpio_0_pins_4_i_ival(gpio_i[4]), + .gpio_0_pins_4_i_po(1'b0), + .gpio_0_pins_4_o_oval(gpio_o[4]), + .gpio_0_pins_4_o_oe(), + .gpio_0_pins_4_o_ie(), + .gpio_0_pins_4_o_pue(), + .gpio_0_pins_4_o_ds(), + .gpio_0_pins_4_o_ps(), + .gpio_0_pins_4_o_ds1(), + .gpio_0_pins_4_o_poe(), + + .gpio_0_pins_5_i_ival(gpio_i[5]), + .gpio_0_pins_5_i_po(1'b0), + .gpio_0_pins_5_o_oval(gpio_o[5]), + .gpio_0_pins_5_o_oe(), + .gpio_0_pins_5_o_ie(), + .gpio_0_pins_5_o_pue(), + .gpio_0_pins_5_o_ds(), + .gpio_0_pins_5_o_ps(), + .gpio_0_pins_5_o_ds1(), + .gpio_0_pins_5_o_poe(), + + .gpio_0_pins_6_i_ival(gpio_i[6]), + .gpio_0_pins_6_i_po(1'b0), + .gpio_0_pins_6_o_oval(gpio_o[6]), + .gpio_0_pins_6_o_oe(), + .gpio_0_pins_6_o_ie(), + .gpio_0_pins_6_o_pue(), + .gpio_0_pins_6_o_ds(), + .gpio_0_pins_6_o_ps(), + .gpio_0_pins_6_o_ds1(), + .gpio_0_pins_6_o_poe(), + + .gpio_0_pins_7_i_ival(gpio_i[7]), + .gpio_0_pins_7_i_po(1'b0), + .gpio_0_pins_7_o_oval(gpio_o[7]), + .gpio_0_pins_7_o_oe(), + .gpio_0_pins_7_o_ie(), + .gpio_0_pins_7_o_pue(), + .gpio_0_pins_7_o_ds(), + .gpio_0_pins_7_o_ps(), + .gpio_0_pins_7_o_ds1(), + .gpio_0_pins_7_o_poe(), + + .uart_0_txd(), + .uart_0_rxd(1'b0), + + .pwm_0_gpio_0(), + .pwm_0_gpio_1(), + .pwm_0_gpio_2(), + .pwm_0_gpio_3(), + + .spi_0_sck(), + .spi_0_dq_0_i(1'b0), + .spi_0_dq_0_o(), + .spi_0_dq_0_ie(), + .spi_0_dq_0_oe(), + .spi_0_dq_1_i(1'b0), + .spi_0_dq_1_o(), + .spi_0_dq_1_ie(), + .spi_0_dq_1_oe(), + .spi_0_dq_2_i(1'b0), + .spi_0_dq_2_o(), + .spi_0_dq_2_ie(), + .spi_0_dq_2_oe(), + .spi_0_dq_3_i(1'b0), + .spi_0_dq_3_o(), + .spi_0_dq_3_ie(), + .spi_0_dq_3_oe(), + .spi_0_cs_0(), + .spi_0_cs_1(), + .spi_0_cs_2(), + .spi_0_cs_3(), + + .i2c_0_scl_in(1'b0), + .i2c_0_scl_out(), + .i2c_0_scl_oe(), + .i2c_0_sda_in(1'b0), + .i2c_0_sda_out(), + .i2c_0_sda_oe(), + .interrupts(2'b0), .cdrio_overCLK(clk400),