From fa45f0fabc4142acbcb91139f5341a1fee6cd464 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 21 May 2024 15:07:39 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BD=BF=E7=94=A8DP=E6=9B=BF=E4=BB=A3=E4=B8=8A?=
 =?UTF-8?q?=E4=B8=8B=E8=A1=8C=E4=BC=AA=E5=8F=8C=E7=AB=AF=E5=8F=A3SRAM?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/BackBoardMst.scala | 50 ++++++++++++---------
 1 file changed, 29 insertions(+), 21 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 4d46362..e133706 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -63,8 +63,8 @@ class BackBoardMstIO extends Bundle{
 class BackBoardMstBase extends Module{ //10M
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
-  val mirrorDown = Module(new MirrorSRAMDown())
-  val mirrorUp   = Module(new MirrorSRAMUp())
+  val mirrorDown = Module(new MirrorSRAMDP())
+  val mirrorUp   = Module(new MirrorSRAMDP())
   val mirrorReg  = Module(new MirrorSRAMDP())
 
   mirrorReg.io.addrB  := DontCare
@@ -88,11 +88,11 @@ class BackBoardMstBase extends Module{ //10M
 
 
 
-  mirrorDown.io.clockr := io.oser_pclk.asBool
-  mirrorDown.io.clockw := io.ides_pclk.asBool //100M  
+  mirrorDown.io.clockA := io.ides_pclk.asBool //100M  
+  mirrorDown.io.clockB := io.oser_pclk.asBool
 
-  mirrorUp.io.clockw := io.oser_pclk.asBool
-  mirrorUp.io.clockr := io.ides_pclk.asBool   //100M
+  mirrorUp.io.clockA := io.ides_pclk.asBool   //100M
+  mirrorUp.io.clockB := io.oser_pclk.asBool
 
   mirrorReg.io.clockA := io.ides_pclk.asBool //100M
   mirrorReg.io.clockB := io.oser_pclk.asBool //10M
@@ -115,24 +115,27 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
     val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
 
-    val isAccessSRAM = ~latchAddr.extract(10) 
-    val isAccessReg  =  latchAddr.extract(10)
+    val isAccessSRAM = ~latchAddr.extract(11) 
+    val isAccessReg  =  latchAddr.extract(11)
+    val isAccessDown = ~latchAddr.extract(10)
     val activeAddr   =  latchAddr(9,0)
 
+    mirrorDown.io.addrA   := activeAddr
+    mirrorDown.io.datawA  := io.FSMC.ADIn
+    mirrorDown.io.enwA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown
+    mirrorDown.io.enrA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown
 
-    mirrorDown.io.enw    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn
-    mirrorDown.io.addrw  := activeAddr
-    mirrorDown.io.dataw  := io.FSMC.ADIn
-
-    mirrorUp.io.enr    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn
-    mirrorUp.io.addrr  := activeAddr
+    mirrorUp.io.addrA   := activeAddr
+    mirrorUp.io.datawA  := io.FSMC.ADIn
+    mirrorUp.io.enwA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown
+    mirrorUp.io.enrA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown
 
     mirrorReg.io.addrA  := activeAddr
     mirrorReg.io.datawA := io.FSMC.ADIn
     mirrorReg.io.enwA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
     mirrorReg.io.enrA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
 
-    io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
+    io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) )
 
 
   }
@@ -611,12 +614,17 @@ with BackBoardMstLVDSError{
     addrr := addrr + 1.U
   }
 
-  mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
-  io.lvdsMst.tx_data_in := mirrorDown.io.datar
-  mirrorDown.io.addrr := addrr
+  mirrorDown.io.enwB := false.B
+  mirrorDown.io.datawB := 0.U
+  mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
+  io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(15,8), mirrorDown.io.datarB(7,0) )
+  mirrorDown.io.addrB := addrr >> 1
   
-  mirrorUp.io.enw   := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast)
-  mirrorUp.io.dataw := io.lvdsMst.rx_data_out
-  mirrorUp.io.addrw := addrw
+
+  val rxData_msb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) )
+  mirrorUp.io.enrB   := false.B
+  mirrorUp.io.enwB   := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0)
+  mirrorUp.io.datawB := (rxData_msb << 8) | io.lvdsMst.rx_data_out 
+  mirrorUp.io.addrB := addrw >> 1
   
 }