From fa28a840ad0f06e1c28d5b1a6a7e041c2440f0cf Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 27 Mar 2024 17:25:53 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E4=B8=8A=E8=A1=8Csram?= =?UTF-8?q?=E8=AF=AD=E6=B3=95=EF=BC=8C=E5=8F=AF=E4=BB=A5=E5=87=8F=E5=B0=91?= =?UTF-8?q?=E8=B5=84=E6=BA=90=EF=BC=8C=E4=BB=BF=E7=9C=9F=E8=BF=87=EF=BC=8C?= =?UTF-8?q?=E4=B8=8A=E7=89=88=E6=9C=AA=E6=B5=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/MirrorSRAM.scala | 27 +++++++---------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala index 9ecc762..551a479 100644 --- a/src/main/scala/backBoard/MirrorSRAM.scala +++ b/src/main/scala/backBoard/MirrorSRAM.scala @@ -216,34 +216,23 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline { | input clockw | ); | - | reg [15:0] ram[0:1023]; + | reg [7:0] ram[0:2047] /* synthesis syn_ramstyle="block_ram" */; | reg [15:0] data_r_reg; | | always @(posedge clockw) begin | if(enw) begin - | if( addrw[0] ) begin - | ram[addrw[10:1]][15:8] <= #1 dataw; - | end else begin - | ram[addrw[10:1]][7:0] <= #1 dataw; - | end - | end + | ram[addrw] <= #1 dataw; + | end | end | - | always @(posedge clockr) begin - | if(enr) begin - | data_r_reg <= #1 ram[addrr]; - | end - | end + | always @(posedge clockr) begin + | if(enr) begin + | data_r_reg <= #1 { ram[2*addrr+1], ram[2*addrr] }; + | end + | end | | assign datar = data_r_reg; | - | initial begin - | for ( integer i = 0; i < 1024; i = i + 1 ) begin - | ram[i] = $random; - | end - | - | data_r_reg = $random; - | end | |endmodule """.stripMargin)