diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala
index 9ecc762..551a479 100644
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -216,34 +216,23 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
       |   input clockw
       |  );
       |  
-      |  	reg [15:0] ram[0:1023];
+      |  	reg [7:0] ram[0:2047] /* synthesis syn_ramstyle="block_ram" */;
       |  	reg [15:0] data_r_reg;
       |  
   		|   always @(posedge clockw) begin
   		|     if(enw) begin
-      |       if( addrw[0] ) begin
-      |         ram[addrw[10:1]][15:8] <= #1 dataw;
-      |       end else begin
-      |         ram[addrw[10:1]][7:0]  <= #1 dataw;
-      |       end				
-  		|   	end
+      |       ram[addrw] <= #1 dataw;
+      |     end
       |   end
       |  
-      |       always @(posedge clockr) begin
-      |  				if(enr) begin
-      |  					data_r_reg <= #1 ram[addrr];
-      |  				end
-      |  			end
+      |   always @(posedge clockr) begin
+      |  		if(enr) begin
+      |  			data_r_reg <= #1 { ram[2*addrr+1], ram[2*addrr] };
+      |  		end
+      |  	end
       |  
       |  	assign datar = data_r_reg;
       |  
-      |  initial begin
-      |  	for ( integer i = 0; i < 1024; i = i + 1 ) begin
-      |  		ram[i] = $random;
-      |  	end
-      |  
-      |  	data_r_reg = $random;
-      |  end
       |   
       |endmodule
     """.stripMargin)