ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

插入一个buf打断时序

Browse Source
This commit is contained in:
RuigeLee
2024-10-22 17:11:56 +08:00
parent 9cc388265c
commit f9d796b067
1 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/main/scala/backBoard/shin/ShinMst.scala
View File

@@ -84,6 +84,8 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
val sendHeader = Reg( new Header_Info_Bundle ) val sendHeader = Reg( new Header_Info_Bundle )
val sendHead = sendHeader.asUInt val sendHead = sendHeader.asUInt
val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt
cdrOut.io.axis <> cdrPendBuf.io.deq
@@ -128,27 +130,27 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
sendStateNext := Mux1H(Seq( sendStateNext := Mux1H(Seq(
(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), (sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (headByte-1).U, 2.U, 1.U ), (sendStateCurr === 1.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (headByte-1).U, 2.U, 1.U ),
(sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (sendHeader.length ) - 1.U, 3.U, 2.U ), (sendStateCurr === 2.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (sendHeader.length ) - 1.U, 3.U, 2.U ),
(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ), (sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
)) ))
sendCntNext := Mux1H(Seq( sendCntNext := Mux1H(Seq(
(sendStateCurr === 0.U) -> 0.U, (sendStateCurr === 0.U) -> 0.U,
(sendStateCurr === 1.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 2.U, sendCntCurr + 1.U, 0.U ), sendCntCurr), (sendStateCurr === 1.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 2.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
(sendStateCurr === 2.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 3.U, sendCntCurr + 1.U, 0.U ), sendCntCurr), (sendStateCurr === 2.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 3.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
)) ))
cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U cdrPendBuf.io.enq.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
cdrOut.io.axis.bits.tdata := cdrPendBuf.io.enq.bits.tdata :=
Mux1H(Seq( Mux1H(Seq(
( sendStateCurr === 1.U ) -> (sendHead << (sendCntCurr << 3)).apply(63,56), ( sendStateCurr === 1.U ) -> (sendHead << (sendCntCurr << 3)).apply(63,56),
( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ), ( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ),
)) ))
cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length - 1.U ) cdrPendBuf.io.enq.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length - 1.U )
cdrOut.io.axis.bits.tuser := false.B cdrPendBuf.io.enq.bits.tuser := false.B
mirrorDown.io.enwB := false.B mirrorDown.io.enwB := false.B
mirrorDown.io.datawB := 0.U mirrorDown.io.datawB := 0.U